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61. 发明申请

US20090231007A1 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF OVERCOMING CLOCK SIGNAL JITTER 失效
标题翻译：半导体集成电路可以覆盖时钟信号抖动
公开(公告)号：US20090231007A1
公开(公告)日：2009-09-17
申请号：US12330287
申请日：2008-12-08
申请人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03K7/02
CPC分类号： H03K5/133 , H03K5/003 , H03K5/156
摘要： A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.
摘要翻译：一种半导体集成电路包括分别通过使用第一参考电压和第二参考电压来提供第一调节电压和第二调节电压的电压提供单元，以及时钟缓冲器单元，其提供在第一调节电压和第二调节电压。

62. 发明申请

US20090206900A1 DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE 审中-公开
标题翻译：占空比校正电路和校正周期的方法
公开(公告)号：US20090206900A1
公开(公告)日：2009-08-20
申请号：US12168560
申请日：2008-07-07
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： H03K3/017
CPC分类号： G11C8/04 , H03K5/1565 , H03K2217/0018
摘要： A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages.
摘要翻译：一种能够降低电流消耗的占空比校正电路，包括用于提供反向偏置电压的反向偏置电压供给电路，其中输入时钟的占空比反映在反向偏置电压上; 以及用于调整输入时钟的占空比并被配置为接收反偏压的缓冲器。

63. 发明申请

US20090128214A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090128214A1
公开(公告)日：2009-05-21
申请号：US12177023
申请日：2008-07-21
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.
摘要翻译：数据接收机包括响应于具有预定相位差的时钟信号而接收数据的多个放大器，并且通过基于反馈数据执行均衡功能来放大接收数据，从而输出放大信号，以及多个锁存器用于锁存输出的放大器。一个放大器接收作为反馈数据的放大信号，来自另一个放大器接收时钟信号，该时钟信号的相位比在一个放大器中接收的时钟信号的相位更先进。

64. 发明申请

US20090128200A1 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器接收器电路
公开(公告)号：US20090128200A1
公开(公告)日：2009-05-21
申请号：US12175224
申请日：2008-07-17
申请人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
发明人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/00 , H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.
摘要翻译：能够控制建立/保持时间的接收机电路包括：第一相位发送单元，被配置为通过在与第一时钟信号同步的同时根据多个检测电平检测输入数据来生成第一输出信号，以及控制第一输入信号的建立/保持时间基于第一偏移电压的电平的输出信号，被配置为根据第一代码来控制第一输出信号的电压电平的电平转换器;以及第二相位发送单元，被配置为接收电平转换器的输出信号作为第二偏移电压，同时与第二时钟信号同步，通过根据检测电平检测输入数据产生第二输出信号，并控制第二输出信号的建立/保持时间。

65. 发明申请

US20090116596A1 LOW POWER, HIGH SPEED RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：低功率，高速接收电路，用于半导体集成电路
公开(公告)号：US20090116596A1
公开(公告)日：2009-05-07
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H04L7/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

66. 发明申请

US20090059703A1 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器接收器电路
公开(公告)号：US20090059703A1
公开(公告)日：2009-03-05
申请号：US12172108
申请日：2008-07-11
申请人： Tae Jin Hwang , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee
发明人： Tae Jin Hwang , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.
摘要翻译：本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间到第一和第二偏移信号。

67. 发明申请

US20080088360A1 Power supply apparatus of semiconductor integrated circuit 失效
标题翻译：半导体集成电路供电装置
公开(公告)号：US20080088360A1
公开(公告)日：2008-04-17
申请号：US11822269
申请日：2007-07-03
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Ic Su Oh , Hee Woong Song , Jong Woon Kim , Tae Jin Hwang
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Ic Su Oh , Hee Woong Song , Jong Woon Kim , Tae Jin Hwang
IPC分类号： G05F5/00
CPC分类号： G06F1/28
摘要： A power supply apparatus of a semiconductor integrated circuit includes a power control device that detects a level of power supplied from the outside and outputs a control signal as information on the detected level, and a power supply device that controls an internal resistance component in response to an input of the control signal, controls the level of the power supplied from the outside, and supplies the power having the controlled level to circuit blocks.
摘要翻译：半导体集成电路的电源装置包括功率控制装置，其检测从外部供给的电力的电平，并输出作为关于检测电平的信息的控制信号;以及电源装置，其响应于控制信号的输入控制从外部提供的电力的电平，并将具有受控电平的电力提供给电路块。

68. 发明授权

US08503251B2 Semiconductor memory device having pipe latch circuit for storing output data during read operation and method for operating the same 有权
标题翻译：具有用于在读取操作期间存储输出数据的管锁存电路的半导体存储器件及其操作方法
公开(公告)号：US08503251B2
公开(公告)日：2013-08-06
申请号：US12881813
申请日：2010-09-14
申请人： Hyung-Soo Kim , Ki-Myung Kyung , Ic-Su Oh , Chang-Kun Park
发明人： Hyung-Soo Kim , Ki-Myung Kyung , Ic-Su Oh , Chang-Kun Park
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/04 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device includes a memory bank configured to output stored data in response to a column selection signal, a plurality of data latching units configured to latch the data outputted from the memory bank in response to an input control signal which is generated according to the column selection signal, and output the latched data in response to an output control signal, a time measurement unit configured to measure a time from an activation of the input control signal to an activation of the output control signal and generate a delay control signal, and an activation control unit configured to control an activation time of the column selection signal in response to the delay control signal.
摘要翻译：一种半导体存储器件，包括响应于列选择信号输出存储数据的存储器组，多个数据锁存单元，用于响应于根据该存储器块生成的输入控制信号，锁存从存储体输出的数据列选择信号，并且响应于输出控制信号输出锁存数据;时间测量单元，被配置为测量从激活输入控制信号到激活输出控制信号的时间，并产生延迟控制信号;以及激活控制单元，被配置为响应于延迟控制信号来控制列选择信号的激活时间。

69. 发明申请

US20130093490A1 INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD 审中-公开
标题翻译：内部电压发生电路及方法
公开(公告)号：US20130093490A1
公开(公告)日：2013-04-18
申请号：US13333043
申请日：2011-12-21
申请人： Hyun Seok KIM , Ic Su OH , Jun Ho LEE , Boo Ho JUNG , Sun Ki CHO , Yang Hee KIM
发明人： Hyun Seok KIM , Ic Su OH , Jun Ho LEE , Boo Ho JUNG , Sun Ki CHO , Yang Hee KIM
IPC分类号： H03L5/00
CPC分类号： H02M3/07 , H02M3/1584
摘要： An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level.
摘要翻译：内部电压产生方法包括以下步骤：通过使用参考电压来设置第一至第三部分; 在第一至第三部分中确定内部电压电平对应于哪个部分; 以及通过根据对应于内部电压电平的部分控制电压抽取量来产生内部电压。

70. 发明授权

US08373456B2 Domain crossing circuit of a semiconductor memory apparatus 有权
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08373456B2
公开(公告)日：2013-02-12
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

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