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61. 发明申请

US20090015862A1 SCANNING METHOD AND SCANNING SYSTEM USING TWAIN DRIVER 有权
标题翻译：使用TWAIN驱动程序的扫描方法和扫描系统
公开(公告)号：US20090015862A1
公开(公告)日：2009-01-15
申请号：US12047607
申请日：2008-03-13
申请人： Dong-keun KIM
发明人： Dong-keun KIM
IPC分类号： G06K15/00 , H04N1/04
CPC分类号： H04N1/00204 , H04N1/00408 , H04N2201/0015 , H04N2201/0039 , H04N2201/0041 , H04N2201/0046 , H04N2201/0075 , H04N2201/0081 , H04N2201/0094
摘要： A scanning method used to scan documents in a scanning system, the system including a scanner and a user host computer having a technology without an interesting name (TWAIN) driver, the scanner and the user host computer connected by a local interface and a network, includes selecting one of the local interface or the network to connect the scanner and the user host computer; if the network is selected, connecting the TWAIN driver to the scanner via the selected network to control scanning processes of the scanner; and performing scanning according to the selected local interface or the network.
摘要翻译：一种用于扫描扫描系统中的文档的扫描方法，该系统包括扫描仪和具有无有趣名称（TWAIN）驱动程序的技术的用户主机，通过本地接口和网络连接的扫描仪和用户主机，包括选择本地接口或网络之一来连接扫描仪和用户主机; 如果选择了网络，则通过所选网络将TWAIN驱动程序连接到扫描仪，以控制扫描仪的扫描过程; 并根据所选择的本地接口或网络执行扫描。

62. 发明申请

US20080212393A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080212393A1
公开(公告)日：2008-09-04
申请号：US11819565
申请日：2007-06-28
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/06
摘要： A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits of the word line driver unit, and outputting the latched first address to the word line driver unit; and an address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the word line driver unit, and outputting a latched second address to the word line driver unit.
摘要翻译：半导体存储器件可以有效地选择字线。半导体存储器件包括字线驱动器单元，用于包括用于驱动单元块的N个字线的N个单位驱动电路，N个单元驱动电路被分成M组驱动电路; 公共地址锁存单元，用于锁存用于选择字线驱动器单元的M组驱动电路中的一个的第一地址，并将锁存的第一地址输出到字线驱动器单元; 以及地址锁存单元，用于锁存用于在字线驱动器单元中选择所选择的组驱动电路的单元驱动电路的第二地址，并将锁存的第二地址输出到字线驱动器单元。

63. 发明申请

US20080002500A1 Semiconductor memory device having bit line equalizer in cell array 有权
标题翻译：具有单元阵列中的位线均衡器的半导体存储器件
公开(公告)号：US20080002500A1
公开(公告)日：2008-01-03
申请号：US11647370
申请日：2006-12-29
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/12 , G11C7/18
摘要： A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.
摘要翻译：半导体存储器件包括至少一个单元阵列和第一和第二位线读出放大单元。单元阵列包括通过信号线彼此连接的多个位线对和多个位线均衡器。每个位线均衡器均衡相应的位线对。第一和第二位线检测放大单元交替地连接到位线对并接收相应的位线均衡信号。

64. 发明申请

US20070133988A1 GPON system and method for bandwidth allocation in GPON system 审中-公开
标题翻译： GPON系统中的GPON系统和带宽分配方法
公开(公告)号：US20070133988A1
公开(公告)日：2007-06-14
申请号：US11592273
申请日：2006-11-03
申请人： Yu-Gun Kim , Byeong-Hoon Kim , Tae-Sung Park , Jeong-Won Park , Jai-Young Park , Jong-Kook Kim , Dong-Keun Kim , Su-Hyung Kim , Jae-Young Lee , Jae-Hyun Kim , Hoon-Jae Yeon
发明人： Yu-Gun Kim , Byeong-Hoon Kim , Tae-Sung Park , Jeong-Won Park , Jai-Young Park , Jong-Kook Kim , Dong-Keun Kim , Su-Hyung Kim , Jae-Young Lee , Jae-Hyun Kim , Hoon-Jae Yeon
IPC分类号： H04J14/00
CPC分类号： H04J3/1694 , H04J14/0226 , H04J14/0247 , H04J14/0252 , H04J14/0282
摘要： In a gigabit-capable passive optical network (GPON) and a method for bandwidth allocation in the GPON system, when an optical network unit (ONU) requests a bandwidth less than its preset minimum bandwidth, the requested bandwidth is allocated to the ONU. When there are traffic-container (T-CONT) classes of ONUs not allocated bandwidth after the requested bandwidth allocation, a spare bandwidth after the requested bandwidth allocation is dynamically allocated to the T-CONT class of each ONU according to a weight of each T-CONT class and a percentage of each T-CONT buffer queue. Thus, in the short term, upstream channel transmission according to T-CONT priority in a congested state can be ensured, and, in the long run, network traffic congestion can be prevented.
摘要翻译：在GPON系统中的千兆位无源光网络（GPON）和带宽分配方法中，当光网络单元（ONU）请求小于其预设最小带宽的带宽时，将所请求的带宽分配给ONU。在所请求的带宽分配后，当没有分配带宽的ONU的业务容器（T-CONT）类别时，根据每个T的权重将请求的带宽分配后的备用带宽动态分配给每个ONU的T-CONT类 -CONT类和每个T-CONT缓冲区队列的百分比。因此，在短期内，可以确保在拥塞状态下根据T-CONT优先级的上行信道传输，并且从长远来看，可以防止网络流量拥塞。

65. 发明申请

US20070126469A1 Device for controlling on die termination 有权
标题翻译：用于控制管芯端接的装置
公开(公告)号：US20070126469A1
公开(公告)日：2007-06-07
申请号：US11477543
申请日：2006-06-30
申请人： Dong-keun Kim , Kyung-Hoon Kim
发明人： Dong-keun Kim , Kyung-Hoon Kim
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an intermediate internal clock signal and an intermediate DLL clock signal in response to the clock control signal; and an ODT control unit for controlling an ODT block by receiving an ODT control signal in response to the intermediate internal clock signal and the intermediate DLL clock signal.
摘要翻译：芯片终端（ODT）控制装置包括：模式寄存器组，用于基于模式集信息产生时钟控制信号; 时钟控制单元，用于接收内部时钟信号和延迟锁定环（DLL）时钟信号，并响应于时钟控制信号输出中间内部时钟信号和中间DLL时钟信号; 以及ODT控制单元，用于响应于中间内部时钟信号和中间DLL时钟信号而接收ODT控制信号来控制ODT块。

66. 发明申请

US20070070777A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070070777A1
公开(公告)日：2007-03-29
申请号：US11528521
申请日：2006-09-28
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/18 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device can reduce a data writing time. The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines. A pair of first local lines id connected to the pair of bit lines by a first switching unit. A pair of second local lines is connected to the pair of first local lines by a second switching unit. A writing driver drives the second local lines using a normal-driving voltage in response to a data signal through a global line. The writing driver drives the second local lines using an over-driving voltage having a higher level than that of the normal-driving voltage during a predetermined period.
摘要翻译：半导体存储器件可以减少数据写入时间。半导体存储器件包括连接到一对位线的位线读出放大器。通过第一切换单元连接到该对位线的一对第一本地线路id。一对第二本地线路通过第二切换单元与一对第一本地线路连接。写入驱动器响应于通过全局线的数据信号，使用正常驱动电压来驱动第二本地线路。写入驱动器在预定时段内使用具有比正常驱动电压高的电平的过驱动电压来驱动第二本地线路。

67. 发明申请

US20070070756A1 Semiconductor memory device sharing sense amplifier 审中-公开
标题翻译：半导体存储器件共享读出放大器
公开(公告)号：US20070070756A1
公开(公告)日：2007-03-29
申请号：US11478118
申请日：2006-06-30
申请人： Dong-Keun Kim , Chang-Ho Do
发明人： Dong-Keun Kim , Chang-Ho Do
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/06 , G11C7/065 , G11C7/18 , G11C8/12 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device contains a reduced number of signal lines of a core area required for data access. The semiconductor memory device includes a sense amplifier for selectively sensing and amplifying data signals on a first pair of bit lines arranged at a first cell array and a second pair of bit lines arranged at a second cell array; a block selection control unit for generating a first selection control signal and a second selection control signal based on an address input for data access; and a control unit for controlling an equalization of voltage levels of the first pair of bit lines and the second pair of bit lines and for determining whether the sense amplifier is connected with the first pair of bit lines or the second pair of bit lines in response to the first selection control signal and the second selection control signal.
摘要翻译：半导体存储器件包含数据访问所需的核心区域的信号线数量减少。半导体存储器件包括用于选择性地感测和放大布置在第一单元阵列的第一对位线上的数据信号和布置在第二单元阵列的第二对位线的读出放大器; 块选择控制单元，用于基于用于数据访问的地址输入产生第一选择控制信号和第二选择控制信号; 以及控制单元，用于控制第一对位线和第二对位线的电压电平的均衡，并且用于确定读出放大器是否响应于第一对位线或第二对位线连接到第一选择控制信号和第二选择控制信号。

68. 发明申请

US20070070755A1 Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof 审中-公开
标题翻译：具有共享位线读出放大器方案的半导体存储器件及其驱动方法
公开(公告)号：US20070070755A1
公开(公告)日：2007-03-29
申请号：US11477324
申请日：2006-06-30
申请人： Dong-Keun Kim , Chang-Ho Do
发明人： Dong-Keun Kim , Chang-Ho Do
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/06 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal.
摘要翻译：半导体存储器件具有共享位线读出放大器。半导体存储器件包括：位线读出放大器，用于放大施加在位线对上的数据; 高位线断路单元，用于响应于高位线断开信号，选择性地将位线读出放大器与上单元阵列的位线对断开; 低位线断开单元，用于响应于较低的位线断开信号，选择性地将位线读出放大器与下单元阵列的位线对断开; 高位线均衡单元，用于响应于较低位线断开信号对上位单元阵列的位线对进行均衡; 以及低位线均衡单元，用于响应于高位线断开信号来均衡下单元阵列的位线对。

69. 发明申请

US20070041258A1 Semiconductor memory device for reducing cell area 有权
标题翻译：用于减少电池面积的半导体存储器件
公开(公告)号：US20070041258A1
公开(公告)日：2007-02-22
申请号：US11589038
申请日：2006-10-30
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
摘要翻译：一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

70. 发明授权

US09535834B2 Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit 有权
标题翻译：电子设备包括具有布置在字线驱动单元的不同侧上的可变电阻存储元件的存储器阵列
公开(公告)号：US09535834B2
公开(公告)日：2017-01-03
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G06F12/08 , G11C13/00 , G11C11/4099 , G11C11/16
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
摘要翻译：电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压阵列第一读取控制单元; 和第二读取控制单元。

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