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    • 61. 发明申请
    • BROADCAST MESSAGING IN PEER TO PEER OVERLAY NETWORK
    • 广泛的消息传递到对等网络
    • US20100195652A1
    • 2010-08-05
    • US12761318
    • 2010-04-15
    • Yutaka TAKEDAHoward BerkeyPayton R. WhiteAttila Vass
    • Yutaka TAKEDAHoward BerkeyPayton R. WhiteAttila Vass
    • H04L12/56
    • H04L12/1854
    • Broadcast messages are efficiently directed to nodes of an overlay network. Broadcast messages include an End ID parameter specifying the range of key values for nodes that should receive the broadcast message. Each node of an overlay network maintains a list of finger nodes and their respective key values. Upon receiving a broadcast message, a node assigns a finger node a new End ID value based upon the End ID value of the broadcast message or the key value of an adjacent finger node. The node compares a finger node's new End ID value with the finger node's key value to determine whether to forward the broadcast message to that finger node. A broadcast message forwarded to a finger node includes an End ID parameter equal to the new End ID value determined for the finger node. Nodes can aggregate response messages from its finger nodes.
    • 广播消息被有效地指向覆盖网络的节点。 广播消息包括指定应该接收广播消息的节点的密钥值的范围的结束ID参数。 覆盖网络的每个节点维护手指节点及其各自的键值的列表。 在接收到广播消息时,节点基于广播消息的结束ID值或相邻手指节点的密钥值来分配手指节点新的结束ID值。 节点将手指节点的新结束ID值与手指节点的键值进行比较,以确定是否将广播消息转发到该手指节点。 转发到手指节点的广播消息包括等于为手指节点确定的新的结束ID值的结束ID参数。 节点可以聚合来自其手指节点的响应消息。
    • 62. 发明申请
    • MULTI-THREADED PARALLEL PROCESSOR METHODS AND APPARATUS
    • 多螺纹并联处理器方法和装置
    • US20100082951A1
    • 2010-04-01
    • US12630775
    • 2009-12-03
    • John P. BatesAttila Vass
    • John P. BatesAttila Vass
    • G06F9/312
    • G06F9/463G06F9/4881
    • A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first and second regions of a processor's local memory, storing code and/or data for a second context in a second region of the local memory, the secondary processor may execute the first context while the second context waits. Code and/or data for the first context may be transferred from the first region to the second and code and/or data for the second context may be transferred from the second region to the first, and the processor may execute the second context during a pause or stoppage of execution of the first context. Alternatively, the code and/or data for the second context may be transferred to another processor's local memory.
    • 处理器系统可以在具有本地存储器的一个或多个处理器上实现多个上下文。 第一和第二上下文的代码和/或数据可以分别同时存储在处理器的本地存储器的第一和第二区域中,在本地存储器的第二区域中存储用于第二上下文的代码和/或数据,次要处理器可以执行 第二个上下文等待的第一个上下文。 用于第一上下文的代码和/或数据可以从第一区域传送到第二区域,并且用于第二上下文的代码和/或数据可以从第二区域传送到第一区域,并且处理器可以在 暂停或停止执行第一个上下文。 或者,用于第二上下文的代码和/或数据可以被传送到另一个处理器的本地存储器。
    • 68. 发明授权
    • Atomic operation involving processors with different memory transfer operation sizes
    • 具有不同内存传输操作大小的处理器的原子操作
    • US07398368B2
    • 2008-07-08
    • US11291306
    • 2005-12-01
    • James E. MarrJohn P. BatesAttila VassTatsuya Iwamoto
    • James E. MarrJohn P. BatesAttila VassTatsuya Iwamoto
    • G06F12/00
    • G06F9/3879G06F9/526G06F2209/521
    • Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.
    • 原子操作可以在具有主存储器和两个或更多个处理器的处理器系统上实现,所述处理器包括在不同大小的寄存器线上操作的功率处理器元件(PPE)和协同处理器元件(SPE)。 包含原语的主存储器地址被划分为奇偶校验字节和两个或多个部分,其中奇偶校验字节包括至少一个位。 奇偶校验字节的值确定两个或多个部分中的哪一个是有效部分,哪些是无效部分。 原始内存大小大于使用PPE进行原子操作的最大大小,小于或等于使用SPE进行原子操作的最大大小。 读取预留和条件写入指令由PPE和SPE使用来访问或更新原子的值。