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61. 发明授权

US11538919B2 Transistors and arrays of elevationally-extending strings of memory cells 有权
公开(公告)号：US11538919B2
公开(公告)日：2022-12-27
申请号：US17182808
申请日：2021-02-23
申请人： Micron Technology, Inc.
发明人： Ramanathan Gandhi , Augusto Benvenuti , Giovanni Maria Paolucci
IPC分类号： H01L29/51
摘要： A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.

62. 发明授权

US11538822B2 Integrated assemblies having metal-containing liners along bottoms of trenches, and methods of forming integrated assemblies 有权
公开(公告)号：US11538822B2
公开(公告)日：2022-12-27
申请号：US16445065
申请日：2019-06-18
申请人： Micron Technology, inc.
发明人： John D. Hopkins , Justin D. Shepherdson , Collin Howder , Jordan D. Greenlee
IPC分类号： H01L27/11582 , H01L27/11556 , H01L21/02 , H01L27/11565 , H01L21/311 , H01L21/285 , H01L27/11519 , H01L29/66 , H01L21/28
摘要： Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

63. 发明授权

US11527623B2 Integrated assemblies and methods of forming integrated assemblies 有权
公开(公告)号：US11527623B2
公开(公告)日：2022-12-13
申请号：US16940852
申请日：2020-07-28
申请人： Micron Technology, Inc.
发明人： Aaron Michael Lowe
IPC分类号： H01L29/40 , H01L21/28 , H01L27/11502 , H01L27/108 , G11C11/22 , G11C5/06 , H01L29/78 , H01L27/06
摘要： Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.

64. 发明授权

US11520069B2 Footwear scanning systems and methods 有权
公开(公告)号：US11520069B2
公开(公告)日：2022-12-06
申请号：US16894484
申请日：2020-06-05
申请人： Battelle Memorial Institute
发明人： A. Mark Jones , David M. Sheen , Stanley L. Owsley, Jr.
IPC分类号： G01R27/04 , G01R27/32 , G01V3/12 , G01N22/00 , H04B1/38 , G01N22/04 , G01N22/02 , G01N33/28 , G01N33/46 , G01N17/00
摘要： Footwear scanning systems and associated methods are described. According to one aspect, a footwear scanning system includes a base, a shuttle configured to rotate beneath the base, wherein the shuttle comprises an antenna array configured to transmit electromagnetic waves through the base into footwear above the base during the rotation of the shuttle and to receive electromagnetic waves reflected from the footwear during the rotation of the shuttle, a transceiver coupled with the antenna array and configured to apply electrical signals to the antenna array to generate the transmitted electromagnetic waves and to receive electrical signals from the antenna array corresponding to the received electromagnetic waves, and processing circuitry configured to process an output of the transceiver corresponding to the received electromagnetic waves to provide information regarding contents within the footwear.

65. 发明授权

US11517952B2 Shear assisted extrusion process 有权
公开(公告)号：US11517952B2
公开(公告)日：2022-12-06
申请号：US16916548
申请日：2020-06-30
申请人： Battelle Memorial Institute
发明人： Vineet V. Joshi , Glenn J. Grant , Curt A. Lavender , Scott A. Whalen , Saumyadeep Jana , David Catalini , Jens T. Darsell
IPC分类号： B21C23/00 , B21C23/04 , B21C29/00 , B21C27/02 , B21C23/21 , B21C23/22 , B21C25/02
摘要： A shear assisted extrusion process for producing cladded materials wherein a cladding material and a material to be cladded are placed in sequence with the cladded material positioned to contact a rotating scroll face first and the material to be cladded second. The two materials are fed through a shear assisted extrusion device at a preselected feed rate and impacted by a rotating scroll face to generate a cladded extrusion product. This process allows for increased through wall strength and decreases the brittleness in formed structures as compared to the prior art.

66. 发明授权

US11515331B2 Integrated assemblies comprising ferroelectric transistors and non-ferroelectric transistors 有权
公开(公告)号：US11515331B2
公开(公告)日：2022-11-29
申请号：US17003813
申请日：2020-08-26
申请人： Micron Technology, Inc.
发明人： Wayne I. Kinney
IPC分类号： H01L27/115 , H01L27/11597 , H01L27/11592 , H01L23/528 , H01L27/1159 , G11C11/22 , H01L29/78 , H01L29/10 , H01L29/08 , H01L29/66 , H01L29/423 , H01L27/1157 , H01L27/11514 , H01L27/11582
摘要： Some embodiments include an integrated assembly having a semiconductor structure extending from a first wiring to a second wiring. A ferroelectric transistor includes a first transistor gate adjacent a first region of the semiconductor structure. A first non-ferroelectric transistor includes a second transistor gate adjacent a second region of the semiconductor structure. The second region of the semiconductor structure is between the first region of the semiconductor structure and the first wiring. A second non-ferroelectric transistor includes a third transistor gate adjacent a third region of the semiconductor structure. The third region of the semiconductor structure is between the first region of the semiconductor structure and the second wiring.

67. 发明授权

US11512847B1 Steam generation apparatuses, processes, and methods 有权
公开(公告)号：US11512847B1
公开(公告)日：2022-11-29
申请号：US16795274
申请日：2020-02-19
申请人： Alan Rose
发明人： Alan Rose
IPC分类号： F22B3/02 , F28D20/00 , F22B1/20
摘要： Steam production apparatuses are provided. The apparatuses can include at least two compartments that are mechanically engaged. Processes for the production of steam are also provided. The processes can include providing liquid water to a reactive material within a first compartment to generate steam within the first compartment; transferring at least some of the steam to a second compartment that is mechanically engaged with the first compartment; and exposing the steam from the first compartment to material within the second compartment that extends when exposed to the steam, the extending of the material reducing the volume of the first compartment.

68. 发明授权

US11508734B2 Integrated assemblies, and methods of forming integrated assemblies 有权
公开(公告)号：US11508734B2
公开(公告)日：2022-11-22
申请号：US17119129
申请日：2020-12-11
申请人： Micron Technology, Inc.
发明人： Amirhasan Nourbakhsh , John K. Zahurak , Sanh D. Tang , Silvia Borsari , Hong Li
IPC分类号： H01L27/108 , H01L29/78 , H01L29/66
摘要： Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

69. 发明授权

US11502006B2 Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure 有权
公开(公告)号：US11502006B2
公开(公告)日：2022-11-15
申请号：US16427878
申请日：2019-05-31
申请人： Micron Technology, Inc.
发明人： Nanae Yokoyama , Ryota Suzuki , Makoto Sato
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/528 , H01L27/092
摘要： Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region, and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.

70. 发明授权

US11488981B2 Array of vertical transistors and method used in forming an array of vertical transistors 有权
公开(公告)号：US11488981B2
公开(公告)日：2022-11-01
申请号：US16934607
申请日：2020-07-21
申请人： Micron Technology, Inc.
发明人： Yi Fang Lee , Jaydip Guha , Lars P. Heineck , Kamal M. Karda , Si-Woo Lee , Terrence B. McDaniel , Scott E. Sills , Kevin J. Torek , Sheng-Wei Yang
IPC分类号： H01L27/12 , H01L21/84 , H01L27/13
摘要： An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

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