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    • 62. 发明授权
    • Semiconductor device structure
    • 半导体器件结构
    • US06940089B2
    • 2005-09-06
    • US10116559
    • 2002-04-04
    • Zhiyuan ChengEugene A. FitzgeraldDimitri A. Antoniadis
    • Zhiyuan ChengEugene A. FitzgeraldDimitri A. Antoniadis
    • H01L21/20H01L21/306H01L21/762H01L29/06H01L29/04H01L31/0328H01L31/0336H01L31/072
    • H01L21/76256H01L21/02381H01L21/0245H01L21/0251H01L21/02532H01L21/02664H01L21/30608
    • A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop Si1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed Si1-yGey layer, strained S1-zGez layer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.
    • 一种制造半导体结构的方法。 根据本发明的一个方面,在第一半导体衬底上沉积第一组分梯度的Si 1-x N Ge x N x缓冲层,其中Ge组合物x从约 零到小于约20%的值。 然后沉积第一蚀刻停止Si 1-y Ge层,其中Ge组分y大于约20%,使得该层是有效的蚀刻停止 。 然后生长第二蚀刻停止层的应变Si。 沉积层结合到第二衬底。 之后,去除第一衬底以释放所述第一蚀刻停止Si 1-y Ge层。 然后在另一步骤中除去剩余的结构以释放第二蚀刻停止层。 根据本发明的另一方面,提供一种半导体结构。 该结构具有要形成半导体器件的层。 半导体结构包括基底,绝缘层,Ge组分大于约15%的弛豫SiGe层,以及选自但不限于应变Si的弛豫Si
    • 63. 发明授权
    • Crystals of the large ribosomal subunit
    • 大核糖体亚基的晶体
    • US06939848B2
    • 2005-09-06
    • US10391491
    • 2003-03-17
    • Thomas A. SteitzPeter B. MooreNenad BanPoul NissenJeffrey Hansen
    • Thomas A. SteitzPeter B. MooreNenad BanPoul NissenJeffrey Hansen
    • C07K14/215A61K38/00G01N33/48G06F17/00G06F19/00
    • C07K14/215C07K2299/00
    • The present invention provides methods for producing high resolution crystals of ribosomes and ribosomal subunits as well as the crystals produced by such methods. The x-ray diffraction patterns of the crystals provided by the present invention are of sufficiently high resolution for determining the three-dimensional structure of ribosomes and ribosomal subunits, for identifying ligand binding sites on ribosomes and ribosomal subunits, and for molecular modeling of ligands which interact with ribosomes and ribosomal subunits. The present invention provides methods for identifying ribosome-related ligands and methods for designing ligands with specific ribosome-binding properties. Thus, the methods of the present invention may be used to produce ligands which are designed to kill or inhibit any specific target organism(s).
    • 本发明提供了生产核糖体和核糖体亚基的高分辨率晶体的方法以及通过这些方法制备的晶体。 由本发明提供的晶体的x射线衍射图具有足够高的分辨率,用于确定核糖体和核糖体亚基的三维结构,用于鉴定核糖体和核糖体亚基上的配体结合位点,以及用于配体的分子模拟 与核糖体和核糖体亚基相互作用。 本发明提供鉴定核糖体相关配体的方法和用于设计具有特定核糖体结合特性的配体的方法。 因此,本发明的方法可用于产生设计用于杀死或抑制任何特定靶生物的配体。
    • 68. 发明授权
    • Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
    • 使用应变表面沟道MOSFET制造CMOS反相器和集成电路的方法
    • US06881632B2
    • 2005-04-19
    • US10611739
    • 2003-07-01
    • Eugene A. FitzgeraldNicole Gerrish
    • Eugene A. FitzgeraldNicole Gerrish
    • H01L21/8238H01L27/092H01L29/10H01L21/336
    • H01L27/0922H01L21/823807H01L27/092H01L29/1054
    • A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    • 一种制造CMOS反相器的方法,包括提供在Si衬底上具有Si衬底,弛豫的Si 1-x Ge 2 x层的异质结构,以及在Si衬底上的应变表面层 所述松弛的Si 1-x Ge x层; 以及将pMOSFET和nMOSFET集成在所述异质结构中,其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一个实施例提供一种制造集成电路的方法,该集成电路包括提供在Si衬底上具有Si衬底,弛豫的Si 1-x N x Ge x Si层的异质结构和应变 层在松弛的Si 1-x Ge层上; 以及在所述异质结构中形成p晶体管和n晶体管,其中所述应变层包括所述n晶体管和所述p晶体管的沟道,并且所述n晶体管和所述p晶体管在CMOS电路中互连。