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61. 发明申请

US20050142851A1 Method of fabricating MIM capacitor 失效
标题翻译：制造MIM电容的方法
公开(公告)号：US20050142851A1
公开(公告)日：2005-06-30
申请号：US11027838
申请日：2004-12-29
申请人： Yung Kim
发明人： Yung Kim
IPC分类号： H01L27/108 , H01L21/02 , H01L23/522 , H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, forming a planarized second insulating layer having a trench exposing a portion of the patterned first metal layer, forming a second metal layer within the trench, forming a first dielectric layer on the second metal layer, forming first via holes exposing the patterned first metal layer, forming first plugs filling the trench and first via holes, forming a third metal layer thereover, forming a second dielectric layer on the third metal layer, forming a patterned fourth metal layer on the second dielectric layer, patterning the second dielectric layer and the third metal layer, forming a planarized third insulating layer having second via holes therein, and forming a patterned fifth metal layer on the third insulating layer.
摘要翻译：提供了一种制造MIM电容器的方法，通过形成双堆叠型电容器来增加电容器的有效面积，通过该方法可以确保单位体积或面积上的较高电容。该方法包括图案化第一金属层，形成具有暴露图案化的第一金属层的一部分的沟槽的平坦化的第二绝缘层，在沟槽内形成第二金属层，在第二金属层上形成第一介电层，形成第一金属层通孔暴露图案化的第一金属层，形成填充沟槽的第一插塞和第一通孔，在其上形成第三金属层，在第三金属层上形成第二介电层，在第二介电层上形成图案化的第四金属层，图案化第二介电层和第三金属层，形成其中具有第二通孔的平坦化第三绝缘层，并在第三绝缘层上形成图案化的第五金属层。

62. 发明申请

US20050142844A1 Method for fabricating metal interconnect in semiconductor device 审中-公开
标题翻译：在半导体器件中制造金属互连的方法
公开(公告)号：US20050142844A1
公开(公告)日：2005-06-30
申请号：US11026916
申请日：2004-12-30
申请人： Yong Ahn
发明人： Yong Ahn
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522
CPC分类号： H01L21/32136 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a metal interconnect in a semiconductor device is disclosed. A disclosed method comprises: forming a via hole by a damascene process in an interlayer dielectric layer on a substrate; depositing a conducting layer on the substrate including the via hole; forming a photoresist pattern on the conducting layer; and forming a metal interconnect using the photoresist pattern as an etching mask, the lower part of the metal interconnect being wider than the upper part thereof.
摘要翻译：公开了一种在半导体器件中制造金属互连的方法。所公开的方法包括：通过镶嵌工艺在衬底上的层间电介质层中形成通孔; 在包括通孔的基板上沉积导电层; 在导电层上形成光致抗蚀剂图案; 并且使用光致抗蚀剂图案形成金属互连作为蚀刻掩模，金属互连的下部比其上部宽。

63. 发明申请

US20050142841A1 Method for forming metal pattern to reduce contact resistivity with interconnection contact 有权
标题翻译：用于形成金属图案以降低具有互连接触的接触电阻率的方法
公开(公告)号：US20050142841A1
公开(公告)日：2005-06-30
申请号：US11024467
申请日：2004-12-30
申请人： Date-Gun Lee
发明人： Date-Gun Lee
IPC分类号： H01L21/283 , H01L21/4763 , H01L21/768 , H01L23/485
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a metal pattern in a semiconductor device which is capable of reducing contact resistivity with an interconnection contact. The method includes forming a tungsten interconnection contact passing through a lower insulating layer on a semiconductor substrate, forming an upper insulating layer covering the interconnection contact, and forming a groove having the same line width as a damascene trench on the upper insulating layer. The method also includes forming a mask spacer on a sidewall of the groove, forming the damascene trench having an inclined bottom profile for exposing a top surface and a portion of a sidewall of the interconnection contact, and forming a metal pattern with which the damascene trench is filled, the metal pattern electrically connected to the interconnection contact.
摘要翻译：一种在能够降低与互连接点的接触电阻率的半导体器件中形成金属图案的方法。该方法包括形成通过半导体衬底上的下绝缘层的钨互连接触，形成覆盖互连接触的上绝缘层，并在上绝缘层上形成具有与镶嵌沟槽相同的线宽的沟槽。该方法还包括在槽的侧壁上形成掩模间隔物，形成具有倾斜底部轮廓的镶嵌槽，用于暴露互连接触件的顶表面和侧壁的一部分，并形成金属图案，通过该金属图案，镶嵌槽被填充，金属图形电连接到互连触点。

64. 发明申请

US20050142833A1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050142833A1
公开(公告)日：2005-06-30
申请号：US11027851
申请日：2004-12-29
申请人： Jung Joo Kim
发明人： Jung Joo Kim
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/44 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522 , H01L29/40
CPC分类号： H01L21/76834 , H01L21/76828 , H01L21/76832
摘要： The present invention provides a Cu line and method of forming the same, by which reliability (e.g., EM, BTS and the like) can be enhanced by replacing SiN by HfOx, which plays a role as a protective layer and/or an etch stop layer on a Cu line, prevents or inhibits galvanic corrosion due to Cu oxide, and inhibits or reduces additional formation of Cu oxide by gathering or scavenging oxygen atoms from —OH, O2, and H2O. The present method includes the steps of forming a trench in an insulating layer on a substrate, forming a planarized Cu layer in the trench, forming a HfOx layer on the planarized Cu layer, and thermally treating the substrate.
摘要翻译：本发明提供一种Cu线及其形成方法，其可以通过用HfO x x替代SiN来提高可靠性（例如，EM，BTS等）的可靠性，其作用为保护层和/或Cu线上的蚀刻停止层防止或抑制由于Cu氧化物引起的电偶腐蚀，并且通过从-OH，O 2 2上的聚集或清除氧原子来抑制或减少附加的Cu氧化物形成， SUB>和H 2 O。本方法包括以下步骤：在衬底上的绝缘层中形成沟槽，在沟槽中形成平坦化的Cu层，在平坦化的Cu层上形成HfO层，并对衬底进行热处理。

65. 发明申请

US20050142825A1 Method of fabricating semiconductor device employing selectivity poly deposition 失效
标题翻译：使用选择性聚合沉积制造半导体器件的方法
公开(公告)号：US20050142825A1
公开(公告)日：2005-06-30
申请号：US11026312
申请日：2004-12-28
申请人： Myung Jung
发明人： Myung Jung
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/665 , H01L21/823814 , H01L21/823835 , H01L29/41783
摘要： A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.
摘要翻译：公开了一种使用选择性聚合物沉积的半导体器件的制造方法。所公开的方法包括在硅衬底的栅极多晶硅和源极/漏极区上沉积选择性多晶硅，以及从沉积的选择性聚硅在栅极和有源区上形成硅化物区域。因此，采用选择性聚合沉积的本发明可以通过降低微型半导体器件中的表面电阻来降低或最小化接触表面电阻并改善半导体器件的电特性。另外，由于栅电极的尺寸变小，本发明可以作为下一代纳米技术的重要组成部分。此外，大量半导体生产系统可以利用现有的设备来及时采用本发明。

66. 发明申请

US20050142794A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050142794A1
公开(公告)日：2005-06-30
申请号：US11024757
申请日：2004-12-30
申请人： Kwan Koh
发明人： Kwan Koh
IPC分类号： H01L21/20 , H01L21/334 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/94
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A method creates semiconductor device in which a storage dielectric film and a storage electrode included in the capacitor is transferred from an inactive region of a semiconductor substrate to the active region thereof, i.e., into a device isolating trench such that the capacitor is prevented from unnecessarily occupying an active region of a semiconductor substrate while maintaining its proper function. In contrast to a conventional device where a capacitor is formed in the active region of the semiconductor substrate, to the capacitor is formed in the inactive region according to this process. Accordingly, the capacitor is able to maintain a trench structure without needing to perform a step of removal of a step height difference, and the active region is minimized in size. Therefore, without having a problem of a step height increase, a finished semiconductor device is able to accommodate modern demands for increased device interpretation.
摘要翻译：一种方法产生半导体器件，其中包括在电容器中的存储电介质膜和存储电极从半导体衬底的无源区转移到其有源区，即，进入器件隔离沟槽，使得不必要地防止电容器在保持其正常功能的同时占据半导体衬底的有源区。与在半导体基板的有源区域形成电容器的常规器件相反，根据该工艺，在非活性区域中形成电容器。因此，电容器能够保持沟槽结构，而不需要执行去除台阶高度差的步骤，并且有源区域的尺寸最小化。因此，没有台阶高度增加的问题，成品半导体器件能够适应现代的增加设备解读的需求。

67. 发明申请

US20050142785A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050142785A1
公开(公告)日：2005-06-30
申请号：US11027841
申请日：2004-12-29
申请人： Ki Bang
发明人： Ki Bang
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/1041 , H01L29/6656 , H01L29/7833
摘要： A method of fabricating a semiconductor device is provided, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a transistor channel area. The method includes forming a gate insulating layer on a semiconductor substrate, forming a channel ion area in the substrate, forming a gate electrode on the gate insulating layer, forming a sidewall insulating layer on the gate electrode, forming lightly doped regions in the substrate adjacent to the channel ion area and aligned with the gate electrode, forming a spacer insulating layer on the sidewall insulating layer, forming spacers on sidewalls of the gate electrode, and forming heavily doped regions in the substrate aligned with the spacer.
摘要翻译：提供一种制造半导体器件的方法，通过使形成具有晶体管沟道区的P / N结的源极/漏极中的电子或空穴密度最小化来减小泄漏电流。该方法包括在半导体衬底上形成栅极绝缘层，在衬底中形成沟道离子区，在栅极绝缘层上形成栅电极，在栅电极上形成侧壁绝缘层，在衬底相邻形成轻掺杂区到沟道离子区域并与栅电极对准，在侧壁绝缘层上形成间隔绝缘层，在栅电极的侧壁上形成间隔物，以及在与衬垫对准的衬底中形成重掺杂区域。

68. 发明申请

US20050142772A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050142772A1
公开(公告)日：2005-06-30
申请号：US11023844
申请日：2004-12-27
申请人： Hak-Dong Kim
发明人： Hak-Dong Kim
IPC分类号： H01L21/336 , H01L21/28 , H01L29/10 , H01L21/8242 , H01L21/8236
CPC分类号： H01L29/105 , H01L21/28167
摘要： Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an oxide layer from a semiconductor substrate; forming a well region in the substrate by performing a first ion implanting process; removing a native oxide layer from the substrate; adjusting a threshold voltage by performing a second ion implanting process on the substrate; and forming a gate oxide layer on the substrate.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件能够通过抑制由离子注入引起的反冲氧的发生而形成薄的高质量栅极氧化物层。制造半导体器件的方法包括以下步骤：从半导体衬底去除氧化物层; 通过执行第一离子注入工艺在衬底中形成阱区; 从衬底去除原生氧化物层; 通过对所述基板执行第二离子注入处理来调整阈值电压; 以及在所述衬底上形成栅极氧化物层。

69. 发明申请

US20050142761A1 Method of fabricating split gate flash memory device 失效
标题翻译：分闸门闪存器件的制作方法
公开(公告)号：US20050142761A1
公开(公告)日：2005-06-30
申请号：US11024724
申请日：2004-12-30
申请人： Jin Jung
发明人： Jin Jung
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a first gate pattern covered with a cap layer on a semiconductor substrate in an active area, and forming an etchant-resistant layer covering one side of the first gate pattern, the etchant-resistant layer extending to a surface of the substrate to cover one confronting side of a neighboring first gate pattern in the active area. The method also includes forming an insulating layer on an exposed surface of the first gate pattern, and forming a second gate pattern covering the first gate pattern and the insulating layer, the second gate pattern not overlapping the etch-resistant layer. The method further includes removing the etch-resistant layer, and forming a pair of doped regions in the substrate aligned with the first and second gate patterns.
摘要翻译：一种制造分裂栅极闪存器件的方法，通过该方法防止了桁条的产生。该方法包括在有源区域中形成在半导体衬底上覆盖有覆盖层的第一栅极图案，以及形成覆盖第一栅极图案的一侧的耐蚀刻层，耐蚀刻层延伸到衬底的表面以覆盖活动区域中相邻的第一栅极图案的相对侧。该方法还包括在第一栅极图案的暴露表面上形成绝缘层，以及形成覆盖第一栅极图案和绝缘层的第二栅极图案，第二栅极图案不与抗蚀刻层重叠。该方法还包括去除耐蚀刻层，以及在与第一和第二栅极图案对准的衬底中形成一对掺杂区域。

70. 发明申请

US20050142757A1 Methods of fabricating nonvolatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20050142757A1
公开(公告)日：2005-06-30
申请号：US11024194
申请日：2004-12-29
申请人： Sang Lee , Jin Jung , Sung Kwon
发明人： Sang Lee , Jin Jung , Sung Kwon
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an active region of the semiconductor substrate to form a well of a high voltage transistor and adjust its threshold voltage, thereby forming a conductive region; depositing an ONO layer on the semiconductor substrate; patterning and etching the ONO layer to form an ONO structure; and forming a gate oxide layer on the semiconductor substrate.
摘要翻译：公开了一种非易失性存储器件的制造方法。所公开的方法包括：将离子注入半导体衬底的有源区以形成低压晶体管的阱并调节其阈值电压; 将离子注入到半导体衬底的有源区中以形成高压晶体管的阱并调整其阈值电压，由此形成导电区; 在半导体衬底上沉积ONO层; 图案化和蚀刻ONO层以形成ONO结构; 以及在所述半导体衬底上形成栅氧化层。

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