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61. 发明授权

US07763494B2 Semiconductor device package with multi-chips and method of the same 有权
标题翻译：半导体器件封装采用多芯片和方法相同
公开(公告)号：US07763494B2
公开(公告)日：2010-07-27
申请号：US12216658
申请日：2008-07-09
申请人： Wen-Kun Yang , Diann-Fang Lin
发明人： Wen-Kun Yang , Diann-Fang Lin
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L2221/68345 , H01L2224/05554 , H01L2224/05647 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29191 , H01L2224/29198 , H01L2224/29298 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/4903 , H01L2224/49051 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2224/83194 , H01L2224/8385 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06555 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01059 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01087 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/09701 , H01L2924/10161 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/0715 , H01L2224/85 , H01L2924/00 , H01L2924/01026 , H01L2924/00012 , H01L2224/32225 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/45099 , H01L2224/05599
摘要： The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.
摘要翻译：本发明提供一种具有多芯片的半导体器件封装，该多芯片包括具有至少一个裸片接收通孔的基板，连接通孔结构和上表面上的第一接触焊盘以及在该基板的下表面上的第二接触焊盘。至少具有第一接合焊盘的第一管芯设置在管芯接收通孔内。第一粘合材料形成在模具下面，第二粘合材料填充在基板的模具和模具的侧壁之间的间隙中。然后，形成第一接合线以耦合第一接合焊盘和第一接触焊盘。此外，具有第二接合焊盘的至少第二管芯被放置在第一管芯上。第二接合线被形成为耦合到第二接合焊盘和第一接触焊盘。介电层形成在第一和第二接合线，第一和第二管芯和基底上。

62. 发明申请

US20090127686A1 Stacking die package structure for semiconductor devices and method of the same 审中-公开
标题翻译：堆叠半导体器件的封装结构及其方法
公开(公告)号：US20090127686A1
公开(公告)日：2009-05-21
申请号：US11984781
申请日：2007-11-21
申请人： Wen-Kun Yang , Chi-Yu Wang , Hsien-Wen Hsu
发明人： Wen-Kun Yang , Chi-Yu Wang , Hsien-Wen Hsu
IPC分类号： H01L23/488 , H01L21/58
CPC分类号： H01L24/82 , H01L24/19 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/73267 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/1035 , H01L2225/1058 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.
摘要翻译：本发明公开了一种用于半导体器件的第一多管芯封装结构，该结构包括具有管接收窗口和形成在其中的互连通孔的衬底; 第一级半导体管芯，其通过背对背方案形成在第二级半导体管芯下方并且在管芯接收窗内，其中第一多管芯封装包括形成在第一级半导体管芯下方的第一级接触焊盘，其具有第一级构建形成在其下方以耦合到第一级半导体管芯的第一焊盘; 形成在所述第二级半导体管芯上的第二级接触焊盘，其上形成有第二级构建层，以耦合到所述第二级半导体管芯的第二接合焊盘; 以及形成在第一层建立层下面的导电凸块。

63. 发明授权

US07534632B2 Method for circuits inspection and method of the same 失效
标题翻译：电路检查方法及其方法
公开(公告)号：US07534632B2
公开(公告)日：2009-05-19
申请号：US11707920
申请日：2007-02-20
申请人： Yu-Shan Hu , Dyi-Chung Hu
发明人： Yu-Shan Hu , Dyi-Chung Hu
IPC分类号： G01R31/26
CPC分类号： H05K1/0269 , H05K3/244 , H05K2203/0361 , H05K2203/1105 , H05K2203/161
摘要： A method for circuit inspection comprises steps of providing a substrate having a conductive line; and forming a metal layer on at least the conductive layer to increase a contrast between the conductive layer and adjacent area for the circuit inspection. The method further comprising removing the metal layer. The metal layer is removed by a mixture of nitric acid, hydrogen peroxide and fluoride boric acid. The metal includes Silver, Nickel or Tin. The deposit metal can be removed by inter diffusion and form intermetallic compounds (for example Cu6Sn5) into the under laying conducting line.
摘要翻译：一种用于电路检查的方法包括提供具有导电线的衬底的步骤; 以及在至少导电层上形成金属层，以增加用于电路检查的导电层和相邻区域之间的对比度。该方法还包括去除金属层。通过硝酸，过氧化氢和氟化硼酸的混合物除去金属层。金属包括银，镍或锡。沉积金属可以通过相互扩散去除，并将金属间化合物（例如Cu 6 Sn 5）形成到下敷导电线中。

64. 发明申请

US20090096093A1 INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF THE SAME 审中-公开
标题翻译：半导体封装的相互连接结构及其相关方法
公开(公告)号：US20090096093A1
公开(公告)日：2009-04-16
申请号：US11939732
申请日：2007-11-14
申请人： Wen-Kun Yang , Hsien-Wen Hsu
发明人： Wen-Kun Yang , Hsien-Wen Hsu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5389 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L2224/04105 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05572 , H01L2224/056 , H01L2224/05644 , H01L2224/05655 , H01L2224/12105 , H01L2224/13 , H01L2224/13099 , H01L2224/73267 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers.
摘要翻译：用于半导体管芯组件的互连结构包括其上形成有RDL的堆积层，形成在其上形成有管芯焊盘的管芯上，其中RDL耦合到管芯焊盘; 隔离基座，其具有附接在所述积层层上的球形开口以暴露所述积层内的球垫; 以及导电球，其放置在隔离基座的球形开口中并附着在积层内的球垫上。

65. 发明申请

US20080274593A1 Semiconductor device package with multi-chips and method of the same 有权
标题翻译：半导体器件封装采用多芯片和方法相同
公开(公告)号：US20080274593A1
公开(公告)日：2008-11-06
申请号：US12216658
申请日：2008-07-09
申请人： Wen-Kun Yang , Diann-Fang Lin
发明人： Wen-Kun Yang , Diann-Fang Lin
IPC分类号： H01L21/58
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L2221/68345 , H01L2224/05554 , H01L2224/05647 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29191 , H01L2224/29198 , H01L2224/29298 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/4903 , H01L2224/49051 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2224/83194 , H01L2224/8385 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06555 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01059 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01087 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/09701 , H01L2924/10161 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/0715 , H01L2224/85 , H01L2924/00 , H01L2924/01026 , H01L2924/00012 , H01L2224/32225 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/45099 , H01L2224/05599
摘要： The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.
摘要翻译：本发明提供一种具有多芯片的半导体器件封装，该多芯片包括具有至少一个裸片接收通孔的基板，连接通孔结构和上表面上的第一接触焊盘以及在该基板的下表面上的第二接触焊盘。至少具有第一接合焊盘的第一管芯设置在管芯接收通孔内。第一粘合材料形成在模具下面，第二粘合材料填充在基板的模具和模具的侧壁之间的间隙中。然后，形成第一接合线以耦合第一接合焊盘和第一接触焊盘。此外，具有第二接合焊盘的至少第二管芯被放置在第一管芯上。第二接合线被形成为耦合到第二接合焊盘和第一接触焊盘。介电层形成在第一和第二接合线，第一和第二管芯和基底上。

66. 发明申请

US20080268647A1 METHOD OF PLASMA ETCHING WITH PATTERN MASK 审中-公开
标题翻译：等离子体蚀刻与图案掩模的方法
公开(公告)号：US20080268647A1
公开(公告)日：2008-10-30
申请号：US12134249
申请日：2008-06-06
申请人： Wen-Kun Yang , Jui-Hsien Chang , Wen-Bin Sun
发明人： Wen-Kun Yang , Jui-Hsien Chang , Wen-Bin Sun
IPC分类号： H01L21/302
CPC分类号： H01L21/321 , H01L21/31144
摘要： The present invention provides a method of plasma etching with pattern mask. There are two different devices in the two section of a wafer, comprising silicon and Gallium Arsenide (GaAs). The Silicon section is for general semiconductor. And the GaAs section is for RF device. The material of pad in the silicon is usually metal, and metal oxide is usually formed on the pads. The metal oxide is unwanted for further process; therefore it should be removed by plasma etching process. A film is attached to the surface of the substrate exposing the area need for etching. Then a mask is attached and aligned onto the film therefore exposing the area need for etching. Then plasma dry etching is applied on the substrate for removing the metal oxide.
摘要翻译：本发明提供了一种使用图案掩模进行等离子体蚀刻的方法。在晶片的两个部分中有两种不同的器件，包括硅和砷化镓（GaAs）。硅部分用于一般半导体。而GaAs部分用于RF器件。硅中的焊盘材料通常是金属，金属氧化物通常形成在焊盘上。金属氧化物对于进一步的处理是不需要的; 因此应该通过等离子体蚀刻工艺去除。将膜附着到衬底的表面，暴露出需要蚀刻的区域。然后将掩模附着并对准到膜上，从而暴露该区域对蚀刻的需要。然后在衬底上施加等离子体干蚀刻以去除金属氧化物。

67. 发明申请

US20080258293A1 SEMICONDUCTOR DEVICE PACKAGE TO IMPROVE FUNCTIONS OF HEAT SINK AND GROUND SHIELD 审中-公开
标题翻译：半导体器件封装提高散热器和接地屏蔽功能
公开(公告)号：US20080258293A1
公开(公告)日：2008-10-23
申请号：US11736461
申请日：2007-04-17
申请人： Wen-Kun YANG , Diann-Fang LIN
发明人： Wen-Kun YANG , Diann-Fang LIN
IPC分类号： H01L23/12 , H01L21/00
CPC分类号： H01L23/552 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2223/6677 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： The present invention provides a package structure and a method for forming the same. The structure comprises a substrate with contact pads and through holes filled with conducting metals for performing heat dissipation and ground shielding A chip with bonding pads is attached on the contact pad by an adhesive with high thermal conductivity to achieve heat dissipation. A RDL is formed on the substrate and the chip to couple the bonding pad and the contact pad formed on the substrate. The structure of present invention can improve the thickness thereof, and the heat dissipation and ground shielding of the structure are enhanced. Furthermore, the structure can achieve package on package (PoP) structure.
摘要翻译：本发明提供一种封装结构及其形成方法。该结构包括具有接触焊盘的基板和填充有用于进行散热和接地屏蔽的导电金属的通孔。具有接合焊盘的芯片通过具有高导热性的粘合剂附接在接触焊盘上以实现散热。在衬底和芯片上形成RDL以耦合形成在衬底上的接合焊盘和接触焊盘。本发明的结构可以提高其结构的厚度，提高结构的散热和接地屏蔽。此外，该结构可以实现封装封装（PoP）结构。

68. 发明申请

US20080237828A1 SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE-SURFACES FOR WLP AND METHOD OF THE SAME 审中-公开
标题翻译：半导体器件封装，其具有接收通孔和双层建立层，用于WLP的两个侧表面及其相同方法
公开(公告)号：US20080237828A1
公开(公告)日：2008-10-02
申请号：US11936596
申请日：2007-11-07
申请人： Wen-Kun YANG
发明人： Wen-Kun YANG
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2221/68318 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01068 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： The present invention discloses a structure of package comprising a substrate with at least one die receiving through holes, a conductive connecting through holes structure and a contact pads on both side of substrate. At least one die is disposed within the die receiving through holes. A first material is formed under the die and second material is formed filled in the gap between the die and sidewall of the die receiving though holes. Dielectric layers are formed on the surface of both side of the die and the substrate. Redistribution layers (RDL) are formed on the both sides and coupled to the contact pads. A protection bases are formed over the RDLs.
摘要翻译：本发明公开了一种包装体的结构，该结构包括具有至少一个模头的基板，该基板具有通孔，导电连接通孔结构和基板两侧的接触焊盘。至少一个模具设置在模具内，接收通孔。第一材料形成在模具下方，并且第二材料形成为填充在模具和接收通孔的模具的侧壁之间的间隙中。电介质层形成在管芯和衬底两侧的表面上。再分布层（RDL）形成在两侧并耦合到接触焊盘。在RDL上形成保护基。

69. 发明申请

US20080230884A1 Semiconductor device package having multi-chips with side-by-side configuration and method of the same 有权
标题翻译：具有并列配置的多芯片的半导体器件封装及其方法
公开(公告)号：US20080230884A1
公开(公告)日：2008-09-25
申请号：US11725827
申请日：2007-03-19
申请人： Wen-Kun Yang , Diann-Fang Lin , Tung-Chuan Wang , Hsien-Wen Hsu , Chih-Ming Chen
发明人： Wen-Kun Yang , Diann-Fang Lin , Tung-Chuan Wang , Hsien-Wen Hsu , Chih-Ming Chen
IPC分类号： H01L23/02 , H01L23/48 , H01L23/04 , H01L23/52
CPC分类号： H01L23/3128 , H01L23/3135 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/50 , H01L2224/05554 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate. A build up layer is form on the lower surface of substrate and the back side of first and second die.
摘要翻译：本发明提供一种具有并排配置的多芯片的半导体器件封装，包括：具有通孔的基板，其中，所述基板具有通孔，连接通孔结构和上表面上的第一接触焊盘;以及第二接触焊盘，基质。具有第一接合焊盘的第一管芯和具有第二接合焊盘的第二管芯分别设置在管芯接收通孔内。第一粘合材料形成在第一模具和第二模具和基板之下，并且第二粘合材料填充在第一和第二模具之间的间隙中以及接收基板的贯穿孔的模具的侧壁。此外，形成接合线以在第二接合焊盘和第一接触焊盘之间在第一接合焊盘和第一接触焊盘之间耦合。在接合线，第一和第二管芯和基板上形成介电层。在基板的下表面和第一和第二模具的背面上形成堆积层。

70. 发明授权

US07423335B2 Sensor module package structure and method of the same 有权
标题翻译：传感器模块的封装结构和方法相同
公开(公告)号：US07423335B2
公开(公告)日：2008-09-09
申请号：US11954087
申请日：2007-12-11
申请人： Wen-Kun Yang , Jui-Hsien Chang
发明人： Wen-Kun Yang , Jui-Hsien Chang
IPC分类号： H01L23/02 , H01L29/22 , H01L29/227 , H01L33/00 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/14618 , H01L24/24 , H01L27/14634 , H01L27/14683 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2924/014 , H01L2924/14 , H04N5/2251 , H04N5/2257 , H01L2924/00
摘要： An image sensor multi-chips package structure, includes a first package including a first chip with image sensors having first bonding pads and micro lens on a first active surface, a first die receiving window and first conductive inter-connecting through holes penetrated from a first upper contact pads on a first upper surface of the first chip to a first lower contact pads on a first lower surface of the first chip, wherein a first upper build up layer on the active surface of the first chip coupling from the first bonding pads to the first upper contact pads; a second package comprising a second chip having second bonding pads on a second active surface, a second die receiving window and second conductive inter-connecting through holes penetrated from a second upper contact pads of a second upper surface of the second chip to a second lower contact pads on a second lower surface of the second chip, wherein a second upper build up layers on the second upper surface for coupling from the second bonding pads to the second upper contact pads, and second lower build up layers under the second lower surface for coupling from the second lower contact pads to terminal pads located under the second lower surface; and inter-connecting structures coupled between the first lower contact pads to the second upper contact pads.
摘要翻译：一种图像传感器多芯片封装结构，包括第一封装，其包括具有第一焊盘和第一有源表面上的微透镜的图像传感器的第一芯片，第一裸片接收窗和第一导电互连通孔，所述第一芯片的第一上表面上的上接触焊盘到所述第一芯片的第一下表面上的第一下接触焊盘，其中所述第一芯片的所述有源表面上的第一上层叠层从所述第一焊盘耦合到第一个上接触垫; 第二封装，包括具有在第二有源表面上的第二接合焊盘的第二芯片，第二管芯接收窗口和从第二芯片的第二上表面的第二上接触焊盘穿入的第二导电互连通孔，所述第二芯片的第二下表面上的接触焊盘，其中在所述第二上表面上的用于从所述第二接合焊盘耦合到所述第二上触点焊盘的第二上层叠层，以及在所述第二下表面下方的第二下堆积层，从所述第二下接触焊盘耦合到位于所述第二下表面下方的端子焊盘; 以及耦合在所述第一下接触焊盘与所述第二上接触焊盘之间的连接结构。

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