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51. 发明授权

US07927959B2 Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权
标题翻译：在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件
公开(公告)号：US07927959B2
公开(公告)日：2011-04-19
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L21/467
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分（435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料湿蚀刻化学。所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

52. 发明授权

US07867911B2 Method for forming pattern using hard mask 失效
标题翻译：使用硬掩模形成图案的方法
公开(公告)号：US07867911B2
公开(公告)日：2011-01-11
申请号：US11823770
申请日：2007-06-28
申请人： Ki-Won Nam , Ky-Hyun Han
发明人： Ki-Won Nam , Ky-Hyun Han
IPC分类号： H01L21/467
CPC分类号： H01L21/0332 , H01L21/32139
摘要： A method for forming a pattern in a semiconductor device includes forming an etch target layer, forming a hard mask over the etch target layer, the hard mask including a multiple-layer stack structure comprising a bottom layer, a transformed layer, and an upper layer, wherein the transformed layer is formed by transforming a surface of the bottom layer. The hard mask and the etch target layer are etched.
摘要翻译：一种用于在半导体器件中形成图案的方法包括形成蚀刻目标层，在蚀刻目标层上形成硬掩模，硬掩模包括多层堆叠结构，该多层堆叠结构包括底层，变换层和上层，其中通过转换底层的表面形成变形层。硬掩模和蚀刻目标层被蚀刻。

53. 发明申请

US20100003828A1 METHODS FOR ADJUSTING CRITICAL DIMENSION UNIFORMITY IN AN ETCH PROCESS WITH A HIGHLY CONCENTRATED UNSATURATED HYDROCARBON GAS 审中-公开
标题翻译：在高浓度不饱和碳氢化合物气体的调和过程中调整关键尺寸均匀性的方法
公开(公告)号：US20100003828A1
公开(公告)日：2010-01-07
申请号：US11946562
申请日：2007-11-28
申请人： Guowen Ding , Changhun Lee , Teh-Tien Su
发明人： Guowen Ding , Changhun Lee , Teh-Tien Su
IPC分类号： H01L21/467
CPC分类号： H01L21/32136
摘要： Methods for etching a metal material layer disposed on a substrate to form features with desired profile and uniform critical dimension (CD) of the features across the substrate. In one embodiment, a method for etching a material layer disposed on a substrate includes providing a substrate having a metal layer disposed on a substrate into an etch reactor, flowing a gas mixture containing at least a halogen containing gas and a passivation gas into the reactor, the passivation gas including a nitrogen containing gas and an unsaturated hydrocarbon gas, wherein the nitrogen gas and the unsaturated hydrocarbon gas and etching the metal layer using a plasma formed from the gas mixture. The CD uniformity could be conveniently, efficiently tuned by the gas ratio, if the concentration of the unsaturated hydrocarbon gas is high enough that the molecular ratio of the unsaturated hydrocarbon gas in the diluent gas times the reactor pressure in milliTorr is greater than 1.25.
摘要翻译：用于蚀刻设置在基底上的金属材料层以形成具有跨越衬底的特征所需轮廓和均匀临界尺寸（CD）的特征的方法。在一个实施例中，用于蚀刻设置在衬底上的材料层的方法包括：将具有设置在衬底上的金属层的衬底提供到蚀刻反应器中，将含有至少含卤素气体和钝化气体的气体混合物流入反应器包括含氮气体和不饱和烃气体的钝化气体，其中氮气和不饱和烃气体使用由气体混合物形成的等离子体蚀刻金属层。如果不饱和烃气体的浓度足够高，稀释气体中的不饱和烃气体的分子比（以毫乇为单位的反应器压力）大于1.25，则可以通过气体比率方便地，有效地调节CD均匀性。

54. 发明申请

US20090263967A1 Method of forming noble metal layer using ozone reaction gas 有权
标题翻译：使用臭氧反应气体形成贵金属层的方法
公开(公告)号：US20090263967A1
公开(公告)日：2009-10-22
申请号：US12318468
申请日：2008-12-30
申请人： Deok-Sin Kil , Kee-Jeung Lee , Young-Dae Kim , Jin-Hyock Kim , Kwan-Woo Do , Kyung-Woong Park , Jeong-Yeop Lee , Ja-Yong Kim
发明人： Deok-Sin Kil , Kee-Jeung Lee , Young-Dae Kim , Jin-Hyock Kim , Kwan-Woo Do , Kyung-Woong Park , Jeong-Yeop Lee , Ja-Yong Kim
IPC分类号： H01L21/467 , H01L21/443
CPC分类号： H01L21/28562 , C23C16/045 , C23C16/18 , C23C16/44 , C23C16/45525 , H01L21/28556 , H01L21/76843 , H01L21/76846 , H01L21/76865 , H01L21/7687 , H01L21/76873 , H01L27/105 , H01L27/11502 , H01L28/65
摘要： A noble metal layer is formed using ozone (O3) as a reaction gas.
摘要翻译：使用臭氧（O 3）作为反应气体形成贵金属层。

55. 发明申请

US20090203210A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20090203210A1
公开(公告)日：2009-08-13
申请号：US12364908
申请日：2009-02-03
申请人： Michihiro Murata
发明人： Michihiro Murata
IPC分类号： H01L21/467 , H01L23/52
CPC分类号： H01L23/522 , H01L21/32135 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.
摘要翻译：即使在金属互连的稀疏布置中，提供了形成具有良好横截面形状的金属互连的方法，而不用担心侧蚀。该方法采用以下结构。用于放置虚设金属互连的区域设置在形成金属互连的区域附近。在虚拟金属互连区域中形成沟槽，然后形成用于金属互连的抗蚀剂图案，使得沟槽上方的抗蚀剂在每单位面积上具有大的表面积。随后通过干蚀刻形成金属互连，其中来自沟槽上方的抗蚀剂的有机成分形成实心侧壁保护膜，从而允许各向异性蚀刻。因此，金属互连可以具有有利的横截面形状。

56. 发明申请

US20090173977A1 Method of MRAM fabrication with zero electrical shorting 有权
标题翻译：零电气短路的MRAM制造方法
公开(公告)号：US20090173977A1
公开(公告)日：2009-07-09
申请号：US12006889
申请日：2008-01-07
申请人： Rongfu Xiao , Chyu-Jiuh Torng , Tom Zhong , Witold Kula
发明人： Rongfu Xiao , Chyu-Jiuh Torng , Tom Zhong , Witold Kula
IPC分类号： H01L43/00 , H01L29/82 , H01L43/12 , H01L21/467
CPC分类号： H01L43/12 , H01L43/08
摘要： An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.
摘要翻译：通过使用Ta硬掩模层和蚀刻的组合，形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。第一蚀刻图案Ta硬掩模，而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC，光致抗蚀剂和Ta残留物，第二功率电平在大约400W至600W之间，继续蚀刻叠层，并在其周围形成保护氧化物蚀刻边的堆叠。最后，使用碳，氢和氧气的蚀刻完成了蚀刻，而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。

57. 发明申请

US20090124084A1 FABRICATION OF SUB-RESOLUTION FEATURES FOR AN INTEGRATED CIRCUIT 审中-公开
标题翻译：一体化电路分解特性的制作
公开(公告)号：US20090124084A1
公开(公告)日：2009-05-14
申请号：US11940121
申请日：2007-11-14
申请人： Elliot Tan , James Jeong
发明人： Elliot Tan , James Jeong
IPC分类号： H01L21/467
CPC分类号： H01L21/76816
摘要： A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set.
摘要翻译：一种用于在集成电路上制造子分辨率特征的方法包括在半导体衬底的电介质层上沉积硬掩模层，图案化硬掩模层以形成限定沟槽的硬掩模结构，通过硬的蚀刻电介质层中的沟槽掩模结构，从而在衬底上形成第一组介电结构，在衬底和第一组电介质结构上沉积共形层，蚀刻保形层以形成邻近第一组电介质结构的间隔物，沉积第二电介质层，从而在衬底上形成第二组电介质结构，并蚀刻间隔物以在第一和第二组的电介质结构之间形成次分辨率沟槽。

58. 发明申请

US20080093710A1 Hard mask arrangement, contact arrangement and methods of patterning a substrate and manufacturing a contact arrangement 有权
标题翻译：硬掩模布置，接触布置以及图案化基板和制造接触布置的方法
公开(公告)号：US20080093710A1
公开(公告)日：2008-04-24
申请号：US11583145
申请日：2006-10-19
申请人： Lars Bach
发明人： Lars Bach
IPC分类号： H01L23/52 , H01L21/467
CPC分类号： H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76816 , H01L21/76897
摘要： An interlayer is disposed on a pattern surface of a substrate. A buried hard mask may be provided on the interlayer. The buried hard mask includes a template opening having a template length along a line axis and a template width perpendicular thereto. The buried hard mask is filled with a fill material. A top mask is provided above the filled buried hard mask. The top mask includes a trim opening crossing the template opening and having a trim width along the line axis that is smaller than the template length. By etching the fill material and the interlayer using the top and buried hard mask a process section of the pattern surface may be exposed such that a target length and width of the process section result from the template and the trim widths. The planar dimensions of the process section may be decoupled from each other.
摘要翻译：中间层设置在基板的图案表面上。可以在中间层上设置掩埋的硬掩模。掩埋的硬掩模包括具有沿着线轴的模板长度和与其垂直的模板宽度的模板开口。埋入的硬掩模填充有填充材料。在填充的掩埋硬掩模上方提供顶部掩模。顶部面罩包括与模板开口相交的修剪开口，并且沿着线轴线具有小于模板长度的修剪宽度。通过使用顶部和掩埋的硬掩模蚀刻填充材料和中间层，可以暴露图案表面的处理部分，使得由模板和修剪宽度产生处理部分的目标长度和宽度。处理部分的平面尺寸可以彼此分离。

59. 发明申请

US20080032508A1 Method and Material For Forming A Double Exposure Lithography Pattern 有权
标题翻译：用于形成双曝光平版印刷图案的方法和材料
公开(公告)号：US20080032508A1
公开(公告)日：2008-02-07
申请号：US11563805
申请日：2006-11-28
申请人： Ching-Yu Chang
发明人： Ching-Yu Chang
IPC分类号： H01L21/467
CPC分类号： H01L21/76816 , G03F7/0035 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.
摘要翻译：光刻图案的方法包括在基底上形成第一材料层; 在所述第一材料层上形成包括至少一个开口的第一图案化抗蚀剂层; 在所述第一图案化抗蚀剂层和所述第一材料层上形成第二材料层; 在所述第二材料层上形成包括其中的至少一个开口的第二图案化抗蚀剂层; 以及蚀刻由第一和第二图案化抗蚀剂层未覆盖的第一和第二材料层。

60. 发明申请

US20080020582A1 Method of forming an opening in a semiconductor device and method of manufacturing a semiconductor device using the same 审中-公开
标题翻译：在半导体器件中形成开口的方法及使用其制造半导体器件的方法
公开(公告)号：US20080020582A1
公开(公告)日：2008-01-24
申请号：US11822058
申请日：2007-07-02
申请人： Keun-Hee Bai
发明人： Keun-Hee Bai
IPC分类号： H01L21/467
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31144 , H01L28/91
摘要： In methods of forming an opening in a semiconductor device and methods of manufacturing a semiconductor device, a mask pattern may be formed on a layer to selectively expose the layer through the mask pattern. The layer may be partially etched using the mask pattern as an etching mask and using a first etching gas including carbon under a silicon-containing gas atmosphere until a lower layer beneath the layer is exposed to form a preliminary opening. The layer may be etched using the mask pattern as an etching mask and using a second etching gas until the lower layer is exposed to form an opening through the layer. The layer may be an insulation layer.
摘要翻译：在形成半导体器件中的开口的方法和制造半导体器件的方法中，可以在层上形成掩模图案，以通过掩模图案选择性地暴露该层。可以使用掩模图案作为蚀刻掩模来部分地蚀刻该层，并且在含硅气体气氛下使用包含碳的第一蚀刻气体直到层下面的下层暴露以形成初步开口。可以使用掩模图案作为蚀刻掩模蚀刻该层，并且使用第二蚀刻气体直到下层暴露以形成通过该层的开口。该层可以是绝缘层。

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