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51. 发明授权

US08711836B2 Synchronization of communication equipment 有权
标题翻译：通讯设备同步
公开(公告)号：US08711836B2
公开(公告)日：2014-04-29
申请号：US13003680
申请日：2009-07-13
申请人： Stephen P. Cooke , Tino Zottola
发明人： Stephen P. Cooke , Tino Zottola
IPC分类号： H04J3/06
CPC分类号： H04J3/0617 , H04J3/0638 , H04J3/0688 , H04L1/242 , H04L7/0008 , H04L12/2865 , H04L12/42 , H04M11/062 , H04Q2213/13039 , H04Q2213/13098 , H04Q2213/13106 , H04Q2213/1319 , H04Q2213/13298 , H04Q2213/1336 , H04Q2213/13389
摘要： Apparatus and methods relating to synchronization of communication equipment are disclosed. Synchronization information received from a bonded communication link can be used to synchronize local and/or remote communication equipment, such as femtocell sites coupled to nodes in a ring network. This may involve isolating a frequency reference signal from a DSL (Digital Subscriber Line) communication link which is a constituent link of a bonded communication link, for example. In a ring network, received synchronization information could be used in synchronizing a locally connected installation of communication equipment, and passed for transmission in the ring network for synchronizing other communication equipment. Such dropping and passing of an analog frequency reference signal could be applied in networks having other topologies as well. At least some embodiments of the invention are applicable to optical links. One or more dedicated wavelengths of an optical link could be used to transfer a frequency reference signal, for example. Other functions, such as quality monitoring, quality reporting, and/or predictive traffic forwarding may be provided in some embodiments.
摘要翻译：公开了与通信设备的同步相关的装置和方法。从绑定通信链路接收的同步信息可用于同步本地和/或远程通信设备，例如耦合到环形网络中的节点的毫微微小区站点。这可以包括例如从作为绑定通信链路的组成链路的DSL（数字用户线路）通信链路隔离频率参考信号。在环网中，接收到的同步信息可以用于同步本地连接的通信设备的设备，并且被传递以在环网中进行传输以同步其他通信设备。模拟频率参考信号的这种丢弃和传递也可以应用于具有其他拓扑的网络中。本发明的至少一些实施例可应用于光链路。例如，光链路的一个或多个专用波长可以用于传送频率参考信号。在一些实施例中可以提供其他功能，例如质量监测，质量报告和/或预测性流量转发。

52. 发明申请

US20110268217A1 SYSTEMS AND METHODS FOR COORDINATING THE SCHEDULING OF BEAMFORMED DATA TO REDUCE INTERFERENCE 有权
标题翻译：协调波束数据调度以减少干扰的系统和方法
公开(公告)号：US20110268217A1
公开(公告)日：2011-11-03
申请号：US12858063
申请日：2010-08-17
申请人： Eamonn Gormley , Chaz Immendorf
发明人： Eamonn Gormley , Chaz Immendorf
IPC分类号： H04L27/00
CPC分类号： H04W72/04 , H04B7/024 , H04B7/0617 , H04J3/0617 , H04J3/0626 , H04L1/205 , H04L5/0007 , H04L5/0035 , H04L25/03343
摘要： A system and method are disclosed for coordinating the scheduling of beamformed data to reduce interference in a wireless system. A first optimum phase adjustment is determined to increase the gain of an intended signal at a mobile device. A second optimum phase adjustment is determined to decrease the gain of interfering signals received at the mobile device. Using a phase adjustment map, a transmission is scheduled at a base station within wireless resources using the first optimum phase adjustment, at the same time an interfering base station is transmitting at the second optimum phase adjustment angle. Thus, signal strength is greatly improved while interference is greatly reduced, improving the efficiency of the wireless system.
摘要翻译：公开了一种用于协调波束形成数据的调度以减少无线系统中的干扰的系统和方法。确定第一最佳相位调整以增加移动设备处的预期信号的增益。确定第二最佳相位调整以减少在移动设备处接收的干扰信号的增益。使用相位调整图，使用第一最佳相位调整在无线资源内的基站处调度发送，同时干扰基站以第二最佳相位调整角度发送。因此，大大降低了信号强度，同时大大降低了干扰，提高了无线系统的效率。

53. 发明授权

US4779268A Frame decoding for digital signal transmission 失效
标题翻译：帧解码用于数字信号传输
公开(公告)号：US4779268A
公开(公告)日：1988-10-18
申请号：US12423
申请日：1987-02-09
申请人： Manfred Wissmann
发明人： Manfred Wissmann
IPC分类号： H04J3/06
CPC分类号： H04J3/0617
摘要： A method and apparatus for frame decoding, in a system which has a series bit data flow with a frame structure including a periodically occurring item of synchronizing information which characterizes the start of each frame, uses a synchronizing bit as synchronizing information. A logic AND-link is perfomed, with data in successive search frames until only one bit, the synchronizing bit, in the search frame is set at logic "1" and this setting is retained for a plurality of search frames. A synchronizing signal, corresponding to the time position of the synchronizing bit, is generated and the bit flow and/or the synchronizing signal are delayed so that the synchronizing signal occurs in synchronism with a delayed bit flow.
摘要翻译：一种用于帧解码的方法和装置，其具有包括表征每帧开始的周期性出现的同步信息项的帧结构的串行比特数据流，使用同步位作为同步信息。执行逻辑AND链接，连续搜索帧中的数据直到搜索帧中的同步位只有一位被设置为逻辑“1”，并且该设置被保留用于多个搜索帧。产生对应于同步位的时间位置的同步信号，并且比特流和/或同步信号被延迟，使得同步信号与延迟比特流同步地发生。

54. 发明授权

US4727558A Method and apparatus for extracting a predetermined bit pattern from a serial bit stream 失效
标题翻译：用于从串行位流中提取预定位模式的方法和装置
公开(公告)号：US4727558A
公开(公告)日：1988-02-23
申请号：US13912
申请日：1987-02-12
申请人： Richard L. Hall
发明人： Richard L. Hall
IPC分类号： H04J3/06 , H04L7/08
CPC分类号： H04J3/0617
摘要： An embedded framing bit pattern in a serial bit stream is located using a sliding compare circuit to determine as each bit of the serial bit stream is received if a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the framing bit pattern match part of the framing bit pattern. A candidate register containing one plus the number of bits between each framing bit is initially preset so that all of the bits are at a first logic state and is sequentially addressed as each bit of the serial bit stream is received. If a match does not occur, then the bit addressed in the candidate register is set to a second logic state, but is not disturbed if a match occurs. The framing bit pattern has been located when the candidate register is addressing the only bit position which is still at the first logic state.
摘要翻译：使用滑动比较电路来定位串行比特流中的嵌入的成帧位模式，以确定如果串行比特流的预定数量的先前比特间隔开所述串行比特流的音调，则确定串行比特流的每个比特被接收成帧位模式匹配帧位模式的一部分。初始设置包含一个加上每个成帧位之间的位数的候选寄存器，使得所有位都处于第一逻辑状态，并且在接收串行位流的每个位时顺序寻址。如果不发生匹配，则将候选寄存器中寻址的位设置为第二逻辑状态，但是如果发生匹配则不会被干扰。当候选寄存器寻址仍处于第一逻辑状态的唯一位位置时，已经定位了成帧位模式。

55. 发明授权

US4688215A Demultiplexer for two-stage framing 失效
标题翻译：解复用器用于两级框架
公开(公告)号：US4688215A
公开(公告)日：1987-08-18
申请号：US741740
申请日：1985-06-05
申请人： Warren R. Fryer
发明人： Warren R. Fryer
IPC分类号： H04J3/06 , H04J3/07 , H04J3/16 , H04L7/00
CPC分类号： H04J3/073 , H04J3/0617 , H04J3/1623
摘要： An apparatus is disclosed for demultiplexing digital signals which utilize two framing sequences, such as the DS1C and DS2 signals of Digital Telephony, to provide framing and pulse stuffing synchronization control information.
摘要翻译：公开了一种用于解复用利用数字电话的DS1C和DS2信号两种成帧序列的数字信号来提供成帧和脉冲填充同步控制信息的装置。

56. 发明授权

US4644536A Method and apparatus for multiplexing digital signals 失效
标题翻译：用于复用数字信号的方法和装置
公开(公告)号：US4644536A
公开(公告)日：1987-02-17
申请号：US630015
申请日：1984-07-12
申请人： Kuniaki Utsumi
发明人： Kuniaki Utsumi
IPC分类号： H04J3/04 , H04J3/06
CPC分类号： H04J3/047 , H04J3/0617 , H04J3/0685
摘要： There is provided a method of multiplexing digital signals which includes multiplexing serial digital signals of a plurality of channels having a given transmission rate and each of which has frame synchronizing signals to a single serial signal, converting signals excluding the frame synchronizing signals of one selected channel to a format which allows inverse-conversion and which does not allow detection of the frame synchronizing signals and using the frame synchronizing signals of the one selected channel as frame synchronizing signals of the single serial signal. There is also provided apparatus for performing the method which includes circuitry for the steps referred to above.
摘要翻译：提供一种复用数字信号的方法，其包括将具有给定传输速率的多个信道的串行数字信号复用并且每个具有帧同步信号到单个串行信号，转换除了一个选定信道的帧同步信号之外的信号以允许逆转换并且不允许检测帧同步信号并且使用一个所选信道的帧同步信号作为单个串行信号的帧同步信号的格式。还提供了用于执行该方法的装置，其包括用于上述步骤的电路。

57. 发明授权

US4622666A Circuits for detecting framing bits in a t.d.m. bit stream 失效
标题翻译：用于检测t.d.m.中的成帧位的电路位流
公开(公告)号：US4622666A
公开(公告)日：1986-11-11
申请号：US680436
申请日：1984-12-10
申请人： Alan F. Graves , Paul A. Littlewood , Johannes S. Weiss
发明人： Alan F. Graves , Paul A. Littlewood , Johannes S. Weiss
IPC分类号： H04J3/06
CPC分类号： H04J3/0617
摘要： A framing circuit is disclosed for detecting framing bits in a t.d.m. bit stream having an extended DS1 framing format. The circuit comprises a RAM for storing in respect of each of the 772 time channels the five most recent information bits of the time channel and three other, candidate, bits which represent the likelihood that the particular time channel carries the framing bit pattern. The current and five stored information bits of each time channel are checked to detect the six-bit framing bit pattern. The candidate bits have their value increased or decreased, within predetermined limits, in dependence upon whether or not a phase of the framing bit pattern is detected, and the updated information and candidate bits are stored in the RAM. The modification of the candidate bits in this manner is effected in only every third 772-bit frame. A framing signal is produced in dependence upon the candidate bits.
摘要翻译：公开了一种用于检测t.d.m中的成帧位的成帧电路。具有扩展的DS1成帧格式的比特流。该电路包括RAM，用于存储772个时间通道中的每一个时钟信道的五个最新信息位以及表示特定时间信道携带成帧位模式的可能性的三个其他候选位。检查每个时间通道的当前和五个存储的信息位以检测六位成帧位模式。根据是否检测到成帧位模式的相位，并且更新的信息和候选比特存储在RAM中，候选比特在其预定限制内增加或减少其值。以这种方式对候选比特的修改仅在每第三个772比特帧中实现。根据候选位产生成帧信号。

58. 发明授权

US4314368A Receiver for pulse code multiplexed signals 失效
标题翻译：接收器用于脉冲码复用信号
公开(公告)号：US4314368A
公开(公告)日：1982-02-02
申请号：US950840
申请日：1978-10-12
申请人： Calvin H. Decoursey , Todd V. Townsend
发明人： Calvin H. Decoursey , Todd V. Townsend
IPC分类号： H04J3/06 , H04J3/12
CPC分类号： H04J3/0617
摘要： Simple and reliable decoding of T-1 type pulse code information is achieved by combining a fast-acting recirculating frame recovery circuit with a simplified signal output register. The frame recovery circuit uses a recirculating 386-bit control word in which all positions which cannot be the main-frame bit position are continuously recorded by the continuous comparison of pairs of incoming data bits spaced 386 bits apart. Following a sufficient number of iterations of the control word to statistically identify all 385 non-main-frame bit positions with a high degree of probability, the remaining unidentified position is read out as the main-frame bit position, and is used to reset the frame clock generator. The signalling pulses recovered from the correctly framed data train are distributed to the proper channel relays by a simplified output circuit which loads the signalling bits into a buffer register at a slow rate dictated by the data train parameters, then unloads the buffer register into the output latches at a rate sufficiently fast to make it impossible for the channel relays to spuriously respond to momentary invalid signals occurring during the unloading process.
摘要翻译：通过将快速作用的循环帧恢复电路与简化的信号输出寄存器组合，实现T-1型脉码信息的简单可靠解码。帧恢复电路使用循环386位控制字，其中不能是主帧位位置的所有位置通过间隔386比特的输入数据位的对的连续比较来连续记录。在控制字的足够数量的迭代之后，以高概率统计地识别所有385个非主帧位位置，剩余的未识别位置被读出作为主帧位位置，并且用于复位帧时钟发生器。从正确成帧的数据序列恢复的信令脉冲通过简化的输出电路分配到适当的信道中继站，该输出电路以数据串参数指定的慢速率将信令位加载到缓冲寄存器中，然后将缓冲寄存器卸载到输出端以足够快的速率锁存，使得信道中继不可能对卸载过程中发生的瞬时无效信号进行虚假的响应。

59. 发明授权

US4214124A Method and device for extracting a synchronizing signal from an incoming PCM signal 失效
标题翻译：从输入PCM信号中提取同步信号的方法和装置
公开(公告)号：US4214124A
公开(公告)日：1980-07-22
申请号：US945223
申请日：1978-09-25
申请人： Daniel J. Jarus
发明人： Daniel J. Jarus
IPC分类号： H04J3/06 , H04L7/10 , H04L7/00
CPC分类号： H04L7/10 , H04J3/0608 , H04J3/0617
摘要： Method and device for extracting a synchronizing signal from a digital signal. The synchronizing signal can be a single bit, a word or a subframe. A first circuit searches for the synchronizing signal in a fixed position in the received signal every time it should occur. If this circuit does not find the synchronizing signal when it should, a second circuit starts a search action for it in the received signal. When the first circuit has not found the synchronizing signal a fixed number of times, the loss of synchronism will be signalled to the equipment that follows. If in the mean time the second circuit has found the synchronizing signal a fixed number of times in the same position in the received signal, then the first circuit will be synchronized with the second circuit. This synchronism only occurs if the second circuit has found the synchronizing signal a greater number of consecutive times than the first circuit within the same period of time.
摘要翻译：从数字信号中提取同步信号的方法和装置。同步信号可以是单个位，字或子帧。第一电路在每次发生时在接收信号中的固定位置搜索同步信号。如果该电路应该没有找到同步信号，则第二个电路在接收到的信号中开始搜索动作。当第一个电路没有发现固定次数的同步信号时，失去同步信号将发送给随后的设备。如果在同一时间内第二电路在接收信号中在同一位置上发现了同步信号的固定次数，则第一电路将与第二电路同步。这种同步仅在第二电路在相同的时间段内发现同步信号比第一电路更多的连续时间的情况下发生。

60. 发明授权

US4010325A Framing circuit for digital signals using evenly spaced alternating framing bits 失效
标题翻译：使用偶数间隔替代框架的数字信号的框架电路
公开(公告)号：US4010325A
公开(公告)日：1977-03-01
申请号：US627323
申请日：1975-10-30
申请人： Ralph LeRoy Kline
发明人： Ralph LeRoy Kline
IPC分类号： H04J3/06 , H04J3/07 , H04J3/12
CPC分类号： H04J3/073 , H04J3/0617 , H04J3/125
摘要： In a digital multiplexer which employs pulse stuffing and a plurality of signaling bits including evenly spaced framing bits, a framing circuit consists essentially of a pair of flip-flops which store the last values of a winking framing signal or the error signal which may have occurred during the framing time slots. Outputs of the flip-flops are connected to gating circuits. One said gate produces an output signal when an error occurs. This error signal is applied to an error density detector. When an out-of-frame condition occurs, i.e., the receiving circuit is considered not to be synchronized with the transmitting circuit, the error density detector output which is applied to a clock pulse generator causes an extended count to occur for each error occurrence. This offsets the bit stream by one time slot for each error following the out-of-frame condition, and this extended count follows the extended count due to the presence of a signaling bit. A control bit generator operates under the control of the reconstructed clock signal, the clock pulse generator, the sample counter, and the framing circuit. When the out-of-frame condition causes an extended count, the control bit generator does not advance. However, the error is cleared by the end of the first time slot following the second extended count. If the winking framing signal is "in frame", the extra count is inhibited. The framing and/or reframing process is accomplished more readily by means of a preview circuit which consists of an additional flip-flop and two additional gates. The flip-flop stores the last value of the bit following the control bit. If the winking framing signal is out of frame and an error occurs, the counters in the control bit clock generator are shifted such that the bit in the additional flip-flop is now the previous framing bit. Thus, the next framing bit must be the opposite to be correct. The additional gates are used to reset or preset the control bit generator so that a predetermined framing bit will be made available to compare with the incoming framing signal.

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