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51. 发明申请

US20080163033A1 ERROR CORRECTION CIRCUIT AND METHOD FOR REDUCING MISCORRECTION PROBABILITY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT 有权
标题翻译：错误校正电路和减少误差概率的方法和包括电路的半导体存储器件
公开(公告)号：US20080163033A1
公开(公告)日：2008-07-03
申请号：US11834844
申请日：2007-08-07
申请人： Yong-Tae YIM
发明人： Yong-Tae YIM
IPC分类号： H03M13/07
CPC分类号： G06F11/1008 , G11C2029/0411 , H03M13/15 , H03M13/3707 , H03M13/3715
摘要： An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encoder generates syndrome data enabling h-bit error correction based on information data and a generator polynomial, where “h” is 2 or an integer greater than 2. The ECC decoder may operate in a single mode for detecting an error position with respect to a maximum of (h−j) bits in the information data based on encoded data including the information and the syndrome data, where “j” is 1 or an integer greater than 1. Alternatively, the ECC decoder may operate in a first operation mode for detecting an error position with respect to a maximum of “h” bits in the information data or in a second operation mode for detecting an error position with respect to a maximum of (h−j) bits in the information data based on encoded data including the information and the syndrome data. Accordingly, the miscorrection probability is reduced, and therefore, data reliability is increased.
摘要翻译：提供了一种用于降低误差概率的纠错电路和方法以及包括该电路的半导体存储器件。误差校正电路包括纠错（ECC）编码器和ECC解码器。 ECC编码器基于信息数据和生成多项式生成校正子数据，其中“h”为2或大于2的整数。ECC解码器可以以单个模式操作，以相对于基于包括信息和校正子数据的编码数据在信息数据中的最大（hj）比特，其中“j”是1或大于1的整数。或者，ECC解码器可以以第一操作模式操作检测相对于信息数据中的最大“h”位的错误位置，或者检测相对于信息数据中的最大（hj）位的错误位置的第二操作模式，基于包括信息的编码数据和综合征数据。因此，误差概率降低，因此数据可靠性增加。

52. 发明申请

US20080109698A1 HYBRID MIN-SUM DECODING APPARATUS WITH LOW BIT RESOLUTION FOR LDPC CODE 审中-公开
标题翻译：用于LDPC码的低位分辨率的混合最小解码器
公开(公告)号：US20080109698A1
公开(公告)日：2008-05-08
申请号：US11550394
申请日：2006-10-17
申请人： HAIYUN YANG , DINESH VENKATACHALAM
发明人： HAIYUN YANG , DINESH VENKATACHALAM
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1102 , H03M13/1117 , H03M13/112 , H03M13/152 , H03M13/155 , H03M13/2732 , H03M13/2906 , H03M13/3715 , H03M13/618 , H03M13/6516 , H03M13/6577 , H03M13/6583
摘要： A new, improved method for mix min-sum decoding using a LDPC code is provided. In order to reconcile the drawbacks of the belief propagation (BP) and min-sum method, but at the same to keep the benefit of same, two major improvements have been proposed in the present invention. In the hardware implementation, due to using fixed-point implementation, it is found the better results lower error floor occurs. The second one has better performance in the range of BER=1e-3 to 1e-6. This invention proposes a method to combine the two improved methods into one, thereby achieving good performances at both cliff region and floor region.
摘要翻译：提供了一种使用LDPC码的混合最小和解码的新的改进方法。为了调和信念传播（BP）和最小和方法的缺点，但是为了保持相同的效果，本发明提出了两个主要的改进。在硬件实现中，由于使用定点实现，发现更好的结果是发生较低的错误发生。第二个在BER = 1e-3到1e-6的范围内具有更好的性能。本发明提出了一种将两种改进方法组合在一起的方法，从而在悬崖区域和地板区域上实现了良好的性能。

53. 发明申请

US20030035389A1 Method and system for utilization of an outer decoder in a broadcast services communication system 有权
标题翻译：在广播业务通信系统中利用外部解码器的方法和系统
公开(公告)号：US20030035389A1
公开(公告)日：2003-02-20
申请号：US09933912
申请日：2001-08-20
发明人： Tao Chen , Jack K. Wolf , Joseph P. Odenwalder , Edward G. Tiedemann JR. , Brian K. Butler , Yongbin Wei
IPC分类号： H04Q007/00
CPC分类号： H03M13/3715 , H03M13/09 , H03M13/2909 , H03M13/293 , H04H20/30 , H04W52/0219 , H04W52/0245 , H04W52/322 , H04W72/005 , Y02D70/1222 , Y02D70/1242
摘要： A Method and System for Utilization of an Outer Decoder in a Broadcast Services Communication System is described. An outer decoder and an inner decoder encode a block of information to be transmitted, to improve protection by adding redundancy. The redundancy permits decoding of the information from less than a complete encoded block of information. Consequently, the receiving station determines when sufficient amount of information for successful decoding has been received, and utilizes the time remaining before the next block of information arrives to perform other activities, e.g., hard handoff on a broadcast channel, inter-frequency hard handoff, and other activities. Alternatively, the receiving station can cease reception, thus decrease power consumption. Furthermore, part of the information block may be utilized for transmission of signaling information.
摘要翻译：描述了在广播业务通信系统中利用外部解码器的方法和系统。外部解码器和内部解码器对要发送的信息块进行编码，以通过增加冗余来改善保护。冗余允许从小于完整编码的信息块解码信息。因此，接收站确定何时已经接收到用于成功解码的信息的足够量，并且利用在下一个信息块到达之前的剩余时间来执行其他活动，例如广播信道上的硬切换，频间硬切换，和其他活动。或者，接收站可以停止接收，从而降低功耗。此外，信息块的一部分可以用于发送信令信息。

54. 发明授权

US12009840B2 Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation 有权
公开(公告)号：US12009840B2
公开(公告)日：2024-06-11
申请号：US17569007
申请日：2022-01-05
申请人： Kioxia Corporation
发明人： Ofir Kanter , Avi Steiner , Yasuhiko Kurosawa
IPC分类号： H03M13/37 , H03M13/01 , H03M13/15 , H03M13/43
CPC分类号： H03M13/3715 , H03M13/3707 , H03M13/015 , H03M13/1575 , H03M13/43
摘要： A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

55. 发明授权

US11817124B2 Composite data recovery procedure 有权
公开(公告)号：US11817124B2
公开(公告)日：2023-11-14
申请号：US17542875
申请日：2021-12-06
申请人： Seagate Technology LLC
发明人： Ara Patapoutian , Jason Charles Jury
IPC分类号： G11B20/18 , G11C29/42 , G11B19/04 , G11C29/52 , H04L43/024 , H03M13/37 , G11B7/09 , G11B20/12
CPC分类号： G11B20/1876 , G11B20/1803 , G06F2211/109 , G11B7/094 , G11B19/041 , G11B20/1258 , G11B20/18 , G11B20/1816 , G11B2020/1222 , G11C29/42 , G11C29/52 , H03M13/3715 , H04L43/024
摘要： A method of recovering data from one or more failed data sectors includes estimating a reader offset position from a first or a second read attempt of the one or more failed data sectors at a current set of channel parameters and basing the estimated reader offset position on, at least in part, a position error signal generated during the first or second read attempt. At least one read is performed on the one or more failed data sectors at the estimated reader offset position to obtain one or more samples. The one or more samples are processed to obtain a processed sample. Iterative outer code recovery is performed on the processed sample.

56. 发明授权

US10630316B2 Bit flipping algorithm for providing soft information during hard decision hard decoding 有权
公开(公告)号：US10630316B2
公开(公告)日：2020-04-21
申请号：US16194374
申请日：2018-11-18
申请人： Silicon Motion Inc.
发明人： Tsung-Chieh Yang , Jian-Dong Du
IPC分类号： H03M13/11 , H03M13/37 , H03M13/45
CPC分类号： H03M13/1108 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/3707 , H03M13/3715 , H03M13/45
摘要： A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.

57. 发明申请

US20190149168A1 SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES 审中-公开
公开(公告)号：US20190149168A1
公开(公告)日：2019-05-16
申请号：US15812808
申请日：2017-11-14
申请人： Nyquist Semiconductor Limited
发明人： Yuan-mao Chang , Jie Chen , Chung-Li Wang
IPC分类号： H03M13/11
CPC分类号： H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/658
摘要： Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a soft decision decoding on a codeword, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a reliability determination for each hard decision and performing a hard decision decoding using the hard decision for each bit and reliability determination for each hard decision.

58. 发明申请

US20190121691A1 DYNAMIC MULTI-STAGE DECODING 审中-公开
公开(公告)号：US20190121691A1
公开(公告)日：2019-04-25
申请号：US15789890
申请日：2017-10-20
申请人： Western Digital Technologies, Inc.
发明人： Jun TAO , Niang-Chu CHEN , Mark Joseph DANCHO , Xiaoheng CHEN
IPC分类号： G06F11/10 , G11C29/52 , H03M13/11
CPC分类号： G06F11/1068 , G11C29/021 , G11C29/028 , G11C29/52 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/6325
摘要： Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

59. 发明申请

US20190097653A1 MEMORY SYSTEM WITH DECODERS AND METHOD OF OPERATING SUCH MEMORY SYSTEM AND DECODERS 审中-公开
公开(公告)号：US20190097653A1
公开(公告)日：2019-03-28
申请号：US16128102
申请日：2018-09-11
申请人： SK hynix memory solutions America Inc.
发明人： Fan ZHANG , Aman BHATIA , Chenrong XIONG , Naveen KUMAR , Yu CAI
IPC分类号： H03M13/11 , H03M13/15 , H03M13/37 , G06F11/10 , G11C29/52 , G11C29/44
CPC分类号： H03M13/1108 , G06F11/1012 , G11C29/14 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , H03M13/1117 , H03M13/112 , H03M13/1575 , H03M13/3707 , H03M13/3715
摘要： A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.

60. 发明申请

US20190087264A1 MEMORY SYSTEM 审中-公开
公开(公告)号：US20190087264A1
公开(公告)日：2019-03-21
申请号：US15916516
申请日：2018-03-09
申请人： Toshiba Memory Corporation
发明人： Tsukasa Tokutomi , Masanobu Shirakawa , Marie Takada , Masamichi Fujiwara , Kazumasa Yamamoto , Naoaki Kokubun , Tatsuro Hitomi , Hironori Uchikawa
IPC分类号： G06F11/10 , H03M13/11 , H03M13/00
CPC分类号： G06F11/1068 , G06F11/1012 , G06F11/1048 , H03M13/1105 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906 , H03M13/3715 , H03M13/6505
摘要： In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

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