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51. 发明申请

US20110148517A1 Shift Register and Driving Method Thereof 有权
标题翻译：移位寄存器及其驱动方法
公开(公告)号：US20110148517A1
公开(公告)日：2011-06-23
申请号：US13039369
申请日：2011-03-03
申请人： Mitsuaki Osame , Aya Anzai
发明人： Mitsuaki Osame , Aya Anzai
IPC分类号： H03H11/00
CPC分类号： H03K5/249 , G11C19/00 , G11C19/184 , H03K5/003 , H03K5/02 , H03K5/082
摘要： A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion, of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided
摘要翻译：低功耗移位寄存器，其输入具有低电压的CK信号，几乎不影响晶体管的特性变化。在本发明中，将逆变器的输入部分设定为阈值电压，并通过电容器装置将CK信号输入到逆变器的输入部分。以这种方式，CK信号被放大，发送到移位寄存器。也就是说，通过获得反相器的阈值电位，可以提供几乎不影响晶体管特性变化的移位寄存器。从移位寄存器的输出脉冲产生CK信号的电平移位器，因此可以提供具有短时间流过直通电流的电平移位器的低功耗移位寄存器

52. 发明授权

US07894561B1 Method and system for providing dynamic DC offset correction 有权
标题翻译：提供动态直流偏移校正的方法和系统
公开(公告)号：US07894561B1
公开(公告)日：2011-02-22
申请号：US11820914
申请日：2007-06-21
申请人： Benjamin C. Buchanan
发明人： Benjamin C. Buchanan
IPC分类号： H04L7/00
CPC分类号： H04L25/061 , H03K5/003
摘要： A method for providing dynamic DC offset correction is provided. The method includes receiving a plurality of uncorrected samples. A determination is made regarding whether a specified number of consecutive uncorrected samples that correspond to a nominal voltage level has been received. When the specified number of consecutive uncorrected samples that correspond to the nominal voltage level has been received, an offset is generated based on an actual voltage level for each of the consecutive uncorrected samples.
摘要翻译：提供了一种用于提供动态DC偏移校正的方法。该方法包括接收多个未校正的样本。确定是否已经接收到与标称电压电平相对应的指定数量的连续未校正样本。当已经接收到对应于额定电压电平的指定数目的连续未校正样本时，基于每个连续未校正样本的实际电压电平产生偏移。

53. 发明授权

US07859352B2 Systems and methods to overcome DC offsets in amplifiers used to start resonant micro-electro mechanical systems 有权
标题翻译：克服用于启动谐振微机电系统的放大器中的直流偏移的系统和方法
公开(公告)号：US07859352B2
公开(公告)日：2010-12-28
申请号：US12252176
申请日：2008-10-15
申请人： Michael Sutton
发明人： Michael Sutton
IPC分类号： H03B5/32 , H01L41/107 , H03L5/00
CPC分类号： H03H9/02409 , G01C19/5776 , H03F3/70 , H03F2200/375 , H03K5/003
摘要： Systems and methods for insuring successful initiation of a resonating micro-electro mechanical systems (MEMS). An example system includes a resonating sensor, a drive device, a charge amplifier, and a voltage gain circuit. At start up, the charge amplifier and voltage gain circuit receives signals from the resonating sensor, compensates this signal for DC offsets, and generates a clock signal for the drive, thus placing the resonating sensor in a steady state operating mode. The circuit includes a plurality of gain switches that are toggled to produce a glitch in the signal associated with the received signal. The glitch overcomes the DC offset. A comparator generates the clock signal for the drive device if a signal associated with the received signal exceeds a reference signal.
摘要翻译：确保共振微机电系统（MEMS）成功启动的系统和方法。示例系统包括谐振传感器，驱动装置，电荷放大器和电压增益电路。在启动时，电荷放大器和电压增益电路接收来自谐振传感器的信号，补偿该信号用于DC偏移，并为驱动器产生时钟信号，从而将谐振传感器置于稳态工作模式。电路包括多个增益开关，其被切换以在与接收信号相关联的信号中产生毛刺。毛刺克服了直流偏移。如果与接收信号相关联的信号超过参考信号，则比较器产生驱动装置的时钟信号。

54. 发明授权

US07848457B2 Constant delay zero standby differential logic receiver and method 有权
标题翻译：恒定延迟零待机差分逻辑接收器和方法
公开(公告)号：US07848457B2
公开(公告)日：2010-12-07
申请号：US11177238
申请日：2005-07-07
申请人： Daniel B. Penney
发明人： Daniel B. Penney
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L25/0274 , H03K5/003 , H03K5/1565 , H03K19/00323 , H04L25/0292 , H04L25/10
摘要： A differential receiver circuit on an integrated circuit consumes substantially no standby power, has constant propagation delay regardless of the input common mode bias, has acceptable common mode rejection and includes first and second pass circuits and buffers to receive differential input signals. The first pass circuit provides a true output signal based on a differential between the “true” buffered signal and the complimentary buffered signal. The second pass circuit provides a “complementary” output signal based on a differential between the complimentary buffered signal and the “true” buffered signal. The differential receiver circuit rejects common mode biases that may be present on the received differential signals without varying propagation delay times.
摘要翻译：集成电路上的差分接收器电路基本上消耗无待机功率，无论输入共模偏置如何，具有恒定的传播延迟，具有可接受的共模抑制，并且包括第一和第二通路电路和缓冲器以接收差分输入信号。第一通电路基于“真实”缓冲信号和互补缓冲信号之间的差分提供真实的输出信号。第二通路电路基于互补缓冲信号和“真实”缓冲信号之间的差分提供“互补”输出信号。差分接收器电路拒绝可能存在于所接收的差分信号上的共模偏置，而不改变传播延迟时间。

55. 发明授权

US07839958B2 System and method for the adjustment of compensation applied to a signal 有权
标题翻译：用于调整应用于信号的补偿的系统和方法
公开(公告)号：US07839958B2
公开(公告)日：2010-11-23
申请号：US11753139
申请日：2007-05-24
申请人： Yasuo Hidaka
发明人： Yasuo Hidaka
IPC分类号： H04B1/10
CPC分类号： H03K5/003 , H03K5/159 , H04B3/145 , H04L25/03885 , H04L25/063
摘要： In one embodiment of the present invention, a method for adjusting a signal includes applying at least one of a loss compensation for frequency-dependent distortion and an offset compensation for DC-offset distortion to a signal before or after the distortion occurs to generate an output signal, the output signal comprising even phase and odd phase. The method also includes selecting either the even phase or the odd phase at which to begin sampling. The method further includes, using a clock signal, beginning at the selected phase, sampling the output signal to generate a plurality of data values and an error value, the error value indicating residue of the distortion based on the sampling of the output signal. The method also includes adjusting none, one, or more of the loss compensation and the offset compensation applied to the signal based on the sampled error value. The method further includes, after adjusting the at least one of the loss compensation and the offset compensation applied to the signal based on the sampled error value, selecting either the even phase or the odd phase at which to begin the next sampling.
摘要翻译：在本发明的一个实施例中，一种用于调整信号的方法包括对失真发生之前或之后的信号施加用于频率相关失真的损耗补偿和DC偏移失真的偏移补偿中的至少一个，以产生输出信号，输出信号包括偶相位和奇相位。该方法还包括选择开始采样的偶相或奇相。该方法还包括使用从所选相位开始的时钟信号，对输出信号进行采样以产生多个数据值和误差值，该误差值表示基于输出信号的采样的失真残差。该方法还包括基于采样的误差值调整施加到信号的损耗补偿和偏移补偿中的一个，或多个。该方法还包括：在根据采样误差值调整施加到信号的损耗补偿和偏移补偿中的至少一个之后，选择开始下一个采样的偶相或奇相。

56. 发明授权

US07834670B2 Input circuit and semiconductor integrated circuit including the same 有权
标题翻译：输入电路和半导体集成电路包括相同
公开(公告)号：US07834670B2
公开(公告)日：2010-11-16
申请号：US12382542
申请日：2009-03-18
申请人： Yuji Nakajima
发明人： Yuji Nakajima
IPC分类号： H01B1/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/505 , H03F2200/453 , H03F2200/456 , H03F2203/45138 , H03F2203/45674 , H03F2203/5021 , H03K5/003
摘要： An input circuit, includes a first buffer circuit having an output signal terminal connected to an output; a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit; a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit; a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit; a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit.
摘要翻译：输入电路包括具有连接到输出的输出信号端的第一缓冲电路; 电容器，其一端连接到输入信号端子，另一端连接到第一缓冲电路的输入端; 接收第一外部电源端子的电压和第二缓冲电路的输出的第一差分放大电路; 接收第二外部电源端子的电压的第二差分放大电路和第三缓冲电路的输出; 第一电阻，其一端连接到第一差分放大电路的输出，另一端连接在电容器和第一缓冲电路之间; 以及第二电阻，其一端连接到第二差分放大电路的输出，另一端连接在电容器和第一缓冲电路之间。

57. 发明授权

US07825714B1 Offset nulling for decreasing offset between currents in a differential signaling system 有权
标题翻译：用于减小差分信号系统中电流之间的偏移量的偏移归零
公开(公告)号：US07825714B1
公开(公告)日：2010-11-02
申请号：US12137984
申请日：2008-06-12
申请人： John B. Groe , Michael Naone Farias , Babak Nejati , Marc Facchini , Thomas Hardin
发明人： John B. Groe , Michael Naone Farias , Babak Nejati , Marc Facchini , Thomas Hardin
IPC分类号： H03L5/00
CPC分类号： H03K19/018528 , H03K5/003 , H03K19/00361
摘要： Systems and methods for nulling offsets in differential signaling systems are described. A first circuit may be configured to sense the difference between a first differential current and a second differential current and provide a sense signal to an adjustment circuit. The adjustment circuit may be configured to generate a correction signal based on the sense signal, where the correction signal is combined with the first differential current to reduce the offset between the first differential current and the second differential current. Alternately, the correction signal may be combined with the first and second differential currents to reduce the offset. The process may be repeated until the corrected first differential current and the second differential current are within a desired tolerance.
摘要翻译：描述了差分信号系统中的零位补偿的系统和方法。第一电路可以被配置为感测第一差分电流和第二差分电流之间的差异，并且向调节电路提供感测信号。调整电路可以被配置为基于感测信号产生校正信号，其中校正信号与第一差分电流组合以减小第一差分电流和第二差分电流之间的偏移。或者，校正信号可以与第一和第二差分电流组合以减小偏移。可以重复该过程，直到校正的第一差分电流和第二差分电流在期望的公差内。

58. 发明授权

US07816971B2 Switch circuit having adjustable linearity of differential mode resistances 有权
标题翻译：开关电路具有可调整的差模电阻的线性度
公开(公告)号：US07816971B2
公开(公告)日：2010-10-19
申请号：US12245401
申请日：2008-10-03
申请人： Chao-Cheng Lee , Ren-Chieh Liu
发明人： Chao-Cheng Lee , Ren-Chieh Liu
IPC分类号： H03K17/16
CPC分类号： H03K5/003 , H03K17/145
摘要： A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches.
摘要翻译：开关电路包括一对金属氧化物半导体（MOS）开关和调节单元。每个MOS开关具有输入端子和输出端子。 MOS开关在其输入端接收一对差分输入电压，并且当MOS开关导通时，在其输出端输出一对差分输出电压。调整单元改变输入端子的共模电平和MOS开关的输出端子之间的差异，以便调节MOS开关的差动模式电阻的线性度。

59. 发明申请

US20100207663A1 SEMICONDUCTOR DEVICE FOR RECEIVING EXTERNAL SIGNAL HAVING RECEIVING CIRCUIT USING INTERNAL REFERENCE VOLTAGE 有权
标题翻译：使用内部参考电压接收外部信号接收电路的半导体器件
公开(公告)号：US20100207663A1
公开(公告)日：2010-08-19
申请号：US12766616
申请日：2010-04-23
申请人： Chang-Ho DO
发明人： Chang-Ho DO
IPC分类号： H03K5/22
CPC分类号： H03K5/1252 , H03K5/003 , H03K5/08 , H04L25/085
摘要： A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.
摘要翻译：一种半导体器件，包括：参考电压生成单元，被配置为通过分压正时钟端子和负时钟端子之间的电压差来产生参考电压;以及逻辑判定单元，被配置为基于所述参考值来确定外部信号的逻辑电平电压。

60. 发明申请

US20100183114A1 Shift Register and Driving Method Thereof 有权
标题翻译：移位寄存器及其驱动方法
公开(公告)号：US20100183114A1
公开(公告)日：2010-07-22
申请号：US12704766
申请日：2010-02-12
申请人： Mitsuaki Osame , Aya Anzai
发明人： Mitsuaki Osame , Aya Anzai
IPC分类号： G11C19/00
CPC分类号： H03K5/249 , G11C19/00 , G11C19/184 , H03K5/003 , H03K5/02 , H03K5/082
摘要： A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this mariner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided
摘要翻译：低功耗移位寄存器，其输入具有低电压的CK信号，几乎不影响晶体管的特性变化。在本发明中，将逆变器的输入部设定为阈值电压，通过电容器装置将CK信号输入到逆变器的输入部。在这个水手中，CK信号被放大，发送到移位寄存器。也就是说，通过获得反相器的阈值电位，可以提供几乎不影响晶体管特性变化的移位寄存器。从移位寄存器的输出脉冲产生CK信号的电平移位器，因此可以提供具有短时间流过直通电流的电平移位器的低功耗移位寄存器

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