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51. 发明申请

US20100062573A1 METHOD FOR PRODUCING AN ELECTRONIC COMPONENT, METHOD FOR PRODUCING A THYRISTOR, METHOD FOR PRODUCING A DRAIN-EXTENDED MOS FILED-EFFECT TRANSISTOR, ELECTRONIC COMPONENT, DRAIN-EXTENDED MOS FIELD-EFFECT TRANSISTOR, ELECTRONIC COMPONENT ARRANGEMENT 有权
标题翻译：用于制造电子元件的方法，用于制造电容器的方法，用于产生漏极扩展MOS填充效应晶体管的方法，电子元件，漏极扩展的MOS场效应晶体管，电子元件布置
公开(公告)号：US20100062573A1
公开(公告)日：2010-03-11
申请号：US12620930
申请日：2009-11-18
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.
摘要翻译：在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域，在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中。

52. 发明授权

US07671366B2 Thin film transistor and organic light emitting device including thin film transistor 有权
标题翻译：薄膜晶体管和有机发光器件包括薄膜晶体管
公开(公告)号：US07671366B2
公开(公告)日：2010-03-02
申请号：US11858863
申请日：2007-09-20
申请人： Joon-Chul Goh
发明人： Joon-Chul Goh
IPC分类号： H01L33/00
CPC分类号： H01L29/42384 , H01L27/12 , H01L27/1229 , H01L27/124 , H01L27/1251 , H01L27/3244 , H01L29/41733 , H01L29/78621 , H01L29/78624
摘要： The present invention relates to a thin film transistor. The thin film transistor includes a semiconductor having first, second, third, fourth, and fifth electrode regions arranged in a direction and spaced apart from each other and first, second, third, and fourth offset regions disposed between the first, second, third, fourth, and fifth electrode regions, respectively. An input electrode is connected to the third electrode region, an output electrode is connected to the first and fifth electrode regions, an insulating layer is disposed on the semiconductor, and a control electrode is disposed on the insulating layer and the second and fourth electrode regions.
摘要翻译：本发明涉及一种薄膜晶体管。薄膜晶体管包括：半导体，其具有沿彼此相隔的方向排列的第一，第二，第三，第四和第五电极区域以及设置在第一，第二，第三和第四偏移区域之间的第一，第二，第三和第四偏移区域，第四和第五电极区域。输入电极连接到第三电极区域，输出电极连接到第一和第五电极区域，绝缘层设置在半导体上，控制电极设置在绝缘层上，第二和第四电极区域。

53. 发明申请

US20090321831A1 PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION 有权
标题翻译：具有金属化源侧HALO区域的部分沉积SOI场效应晶体管
公开(公告)号：US20090321831A1
公开(公告)日：2009-12-31
申请号：US12554344
申请日：2009-09-04
申请人： Jin Cai , Wilfried Haensch , Amlan Majumdar
发明人： Jin Cai , Wilfried Haensch , Amlan Majumdar
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/458 , H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
摘要翻译：源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

54. 发明授权

US07629610B2 Semiconductor display device 失效
标题翻译：半导体显示装置
公开(公告)号：US07629610B2
公开(公告)日：2009-12-08
申请号：US12167575
申请日：2008-07-03
申请人： Shunpei Yamazaki , Jun Koyama
发明人： Shunpei Yamazaki , Jun Koyama
IPC分类号： H01L31/20
CPC分类号： H01L27/1214 , G09G3/2018 , G09G3/2022 , G09G3/3233 , G09G3/3258 , G09G3/3275 , G09G2300/0426 , G09G2300/0809 , G09G2300/0819 , G09G2300/0861 , G09G2310/027 , G09G2320/0285 , G09G2320/029 , G09G2320/043 , G09G2320/045 , G09G2330/021 , G09G2360/142 , G09G2360/145 , G09G2360/148 , G09G2360/16 , H01L27/14678 , H01L27/3211 , H01L27/3246 , H01L27/3269 , H01L27/3295 , H01L29/4908 , H01L29/78624 , H01L51/5271 , H01L2251/5315
摘要： To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels each have a diode. The luminance of the EL elements of each in the display pixels is controlled in accordance with the amount of electric current flowing in each of the diodes.
摘要翻译：为了提供能够显示具有清晰度和期望颜色的图像的半导体显示装置，即使当EL层的劣化速度受其环境的影响时。 EL显示器的显示像素和传感器像素各自具有EL元件，并且传感器像素各自具有二极管。根据在每个二极管中流动的电流量来控制显示像素中的每一个的EL元件的亮度。

55. 发明授权

US07566625B2 Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method 有权
公开(公告)号：US07566625B2
公开(公告)日：2009-07-28
申请号：US10625737
申请日：2003-07-24
申请人： Koji Dairiki
发明人： Koji Dairiki
IPC分类号： H01L21/336
CPC分类号： H01L21/02672 , H01L21/2022 , H01L21/2026 , H01L21/324 , H01L27/1277 , H01L29/66757 , H01L29/78621 , H01L29/78624
摘要： For manufacture of a semiconductor device using a low heat resistant substrate such as a glass substrate, a method of heat treatment for activating an impurity element that is used to dope a semiconductor film and for performing gettering on the semiconductor film in a short period of time without deforming the substrate, is provided. Also provided is a heat treatment apparatus for carrying out the above heat treatment. The heat treatment method of the present invention involves irradiating an object with light emitted from a lamp light source, and is characterized in that the lamp light source emits light for 0.1 to 20 seconds at a time and that light from the lamp light source irradiates the object several times. The method is also characterized in that the irradiated region is subjected to pulsating light from the lamp light source such that the irradiated region holds the temperature to its highest for 0.5 to 5 seconds. The method is also characterized in that the amount of coolant to be supplied is increased or reduced in accordance with blinking of the lamp light source to enhance the effect of the heat treatment on the semiconductor film and to prevent a heat-induced damage to the substrate.

56. 发明授权

US07514714B2 Thin film power MOS transistor, apparatus, and method 有权
标题翻译：薄膜功率MOS晶体管，装置和方法
公开(公告)号：US07514714B2
公开(公告)日：2009-04-07
申请号：US11355937
申请日：2006-02-16
申请人： Ming Fang , Fuchao Wang
发明人： Ming Fang , Fuchao Wang
IPC分类号： H01L27/108 , H01L29/04 , H01L29/12 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/78624 , H01L29/086 , H01L29/42368 , H01L29/7824
摘要： A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N− regions), and the second doped region could represent a p-type region (such as a P− region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.
摘要翻译：薄膜功率晶体管包括在衬底上的多个第一掺杂区域和形成主体的第二掺杂区域。身体的至少一部分设置在多个第一掺杂区域之间。薄膜功率晶体管还包括在衬底上的栅极。薄膜功率晶体管还包括介电层，其至少一部分设置在（i）栅极和（ii）第一和第二掺杂区域之间。此外，薄膜功率晶体管包括接触多个第一掺杂区域的多个触点，其中多个第一掺杂区域形成薄膜功率晶体管的源极和漏极。第一掺杂区域可以表示n型区域（例如N区域），并且第二掺杂区域可以表示p型区域（例如P-区域）。第一掺杂区域也可以表示p型区域，第二掺杂区域可以表示n型区域。

57. 发明授权

US07485898B2 Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07485898B2
公开(公告)日：2009-02-03
申请号：US11799369
申请日：2007-05-01
申请人： Setsuo Nakajima , Hisashi Ohtani , Shunpei Yamazaki
发明人： Setsuo Nakajima , Hisashi Ohtani , Shunpei Yamazaki
IPC分类号： H01L27/15
CPC分类号： G02B27/017 , G02B2027/0138 , G02F1/13454 , H01L27/124 , H01L27/3244 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78624 , H01L29/78627
摘要： Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.
摘要翻译：需要获得同时防止OFF电流增加和导通电流劣化的晶体TFT。晶体TFT的栅电极由形成为与第一栅电极和栅极绝缘膜接触形成的第一栅电极和第二栅极构成。通过使用第一栅电极作为掩模形成LDD区，并且通过使用第二栅极作为掩模形成源区和漏区。通过去除第二栅电极的一部分，获得其中LDD区和第二栅极与其间插入栅极绝缘膜重叠的区域以及LDD区和第二栅电极不重叠的区域的结构。

58. 发明授权

US07470956B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07470956B2
公开(公告)日：2008-12-30
申请号：US11395772
申请日：2006-03-31
申请人： Tetsuya Takahashi
发明人： Tetsuya Takahashi
IPC分类号： H01L29/72
CPC分类号： H01L29/861 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/7394 , H01L29/7824 , H01L29/78624 , H01L29/868
摘要： A semiconductor device has a semiconductor base, an anode electrode, and a cathode electrode. The semiconductor base includes a P type semiconductor substrate, an insulating film, an N− type semiconductor region formed on the insulating film, an N+ type semiconductor region, and a P+ type semiconductor region facing the N+ type semiconductor region via the N− type semiconductor region. The semiconductor device further has an N type diffusion layer which is formed, in the N− type semiconductor region at the interface between the insulating film and the N− type semiconductor region, so as to have a concentration gradient such that the N type impurity concentration increases from the side of the anode electrode to the side of the cathode electrode.
摘要翻译：半导体器件具有半导体基底，阳极电极和阴极电极。半导体基底包括P型半导体衬底，绝缘膜，形成在绝缘膜上的N-型半导体区域，N +型半导体区域和经由N型半导体面向N +型半导体区域的P +型半导体区域地区。半导体器件还具有N型扩散层，其在绝缘膜和N-型半导体区域之间的界面处的N型半导体区域中形成为具有使N型杂质浓度从阳极侧到阴极侧增加。

59. 发明授权

US07462866B2 Electro-optical device and manufacturing method thereof 有权
标题翻译：电光装置及其制造方法
公开(公告)号：US07462866B2
公开(公告)日：2008-12-09
申请号：US11438939
申请日：2006-05-23
申请人： Shunpei Yamazaki
发明人： Shunpei Yamazaki
IPC分类号： H01L29/04
CPC分类号： H01L27/1214 , G02F1/13454 , H01L29/66757 , H01L29/78621 , H01L29/78624 , H01L29/78627 , H01L29/78645 , H01L29/78675 , H01L2029/7863
摘要： An electro-optical device having high operation performance and reliability, and a manufacturing method thereof A TFT structure which is strong agains hot carrier injection is realized by disposing a Lov region 207 in an n-channel TFT 203 which forms a driver circuit. Further, Loff regions 217 to 220 and offset region are disposed in an n-channel TFT 304 which forms a pixel section, and a TFT structure of low OFF current value is realized. Further, by reducing the n-type impurity element contained in Loff regions 217 to 220 to approximately 1×1016 to 5×1018 atoms/cm3, further reduction of OFF current can be performed.
摘要翻译：具有高操作性能和可靠性的电光装置及其制造方法通过在形成驱动电路的n沟道TFT 203中设置Lov区207来实现再次强热载流子注入的TFT结构。此外，在形成像素部的n沟道TFT 304中设置有Loff区域217〜220以及偏移区域，实现了低截止电流值的TFT结构。此外，通过将Loff区域217至220中包含的n型杂质元素减少至约1×1016至5×1018原子/ cm3，可以进一步减少OFF电流。

60. 发明申请

US20080290422A1 ASYMMETRIC FIELD EFFECT TRANSISTORS (FETs) 有权
标题翻译：非对称场效应晶体管（FET）
公开(公告)号：US20080290422A1
公开(公告)日：2008-11-27
申请号：US12169068
申请日：2008-07-08
申请人： Edward J. Nowak
发明人： Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/785 , H01L29/7856 , H01L29/78624
摘要： A semiconductor structure. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and (d) a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material; and (e) a gate stack in direct physical contact with the semiconductor channel region.
摘要翻译：半导体结构。该结构包括（a）半导体沟道区，（b）与半导体沟道区直接物理接触的半导体源块; （c）与半导体源极块直接物理接触的源极接触区域，其中源极接触区域包括第一导电材料，并且其中半导体源极块将源极接触区域与半导体沟道区域物理隔离，并且（d ）与所述半导体沟道区域直接物理接触的漏极接触区域，其中所述半导体沟道区域设置在所述半导体源极块和所述漏极接触区域之间，并且其中所述漏极接触区域包括第二导电材料; 和（e）与半导体沟道区直接物理接触的栅叠层。

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