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51. 发明授权

US09385133B2 Semiconductor device including memory cell with transistors disposed in different active regions 有权
公开(公告)号：US09385133B2
公开(公告)日：2016-07-05
申请号：US14921038
申请日：2015-10-23
申请人： Renesas Electronics Corporation
发明人： Masao Morimoto , Noriaki Maeda , Yasuhisa Shimazaki
IPC分类号： H01L27/11 , H01L27/02 , G11C11/412 , G06F17/50
CPC分类号： H01L27/1116 , G06F17/5072 , G11C11/412 , H01L23/528 , H01L27/0207 , H01L27/0928 , H01L27/1104
摘要： A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

52. 发明授权

US09385127B2 Method and apparatus for suppressing metal-gate cross-diffusion in semiconductor technology 有权
标题翻译：用于抑制半导体技术中金属栅极交叉扩散的方法和装置
公开(公告)号：US09385127B2
公开(公告)日：2016-07-05
申请号：US13973616
申请日：2013-08-22
申请人： Xilinx, Inc.
发明人： Qi Lin , Hong-Tsz Pan , Yun Wu , Bang-Thu Nguyen
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238
CPC分类号： H01L27/0928 , H01L21/8238 , H01L21/823842 , H01L21/823871 , H01L27/092
摘要： An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.
摘要翻译：反相器包括：PMOS，包括：p型源极区域，p型漏极区域，p型源极区域和p型漏极区域之间的p沟道区域以及PMOS金属栅极区域; NMOS，包括：n型源极区域，n型漏极区域，n型源极区域和n型漏极区域之间的n沟道区域以及NMOS金属栅极区域; 在p沟道区域和n沟道区域上方的绝缘层，其中PMOS金属栅极区域和NMOS金属栅极区域在绝缘层之上; 以及NMOS金属栅极区域和PMOS金属栅极区域之间的栅极接触。

53. 发明授权

US09379101B2 Semiconductor integrated circuit device 有权
公开(公告)号：US09379101B2
公开(公告)日：2016-06-28
申请号：US14684323
申请日：2015-04-10
申请人： SOCIONEXT INC.
发明人： Koichi Taniguchi , Masato Maede
IPC分类号： H01L27/02 , H01L23/544 , H01L27/092
CPC分类号： H01L27/0292 , H01L23/50 , H01L23/528 , H01L23/544 , H01L27/0207 , H01L27/0928 , H01L29/0619 , H01L29/0623 , H01L2924/0002 , H03K3/354 , H01L2924/00
摘要： In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

54. 发明申请

US20160181263A1 NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME 审中-公开
公开(公告)号：US20160181263A1
公开(公告)日：2016-06-23
申请号：US15041267
申请日：2016-02-11
申请人： Microsemi SoC Corporation
发明人： Fethi Dhaoui , John McCollum
IPC分类号： H01L27/115 , H01L29/78 , H01L29/08 , H01L29/06 , H01L29/66 , H01L21/265 , H01L21/8238 , H01L21/28 , H01L21/324 , H01L27/092 , H01L21/762
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/3418 , H01L21/26513 , H01L21/28035 , H01L21/324 , H01L21/76224 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L23/528 , H01L27/092 , H01L27/0928 , H01L27/2436 , H01L29/0649 , H01L29/0847 , H01L29/167 , H01L29/66575 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.

55. 发明授权

US09349732B2 High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region 有权
公开(公告)号：US09349732B2
公开(公告)日：2016-05-24
申请号：US14672865
申请日：2015-03-30
申请人： International Business Machines Corporation
发明人： John B. Campi, Jr. , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Souvick Mitra , Mujahid Muhammad
IPC分类号： H01L27/092 , H01L29/10 , H01L29/08 , H01L29/78 , H01L29/66
CPC分类号： H01L27/0928 , H01L21/761 , H01L21/823814 , H01L21/823892 , H01L27/092 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1045 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7801 , H01L29/7816 , H01L29/7835
摘要： Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

56. 发明申请

US20160093694A1 METHODS AND APPARATUSES INCLUDING AN ACTIVE AREA OF A TAP INTERSECTED BY A BOUNDARY OF A WELL 有权
公开(公告)号：US20160093694A1
公开(公告)日：2016-03-31
申请号：US14502804
申请日：2014-09-30
申请人： Micron Technology, Inc.
发明人： Michael Smith
IPC分类号： H01L29/06 , H01L29/36 , H01L29/10 , H01L21/265 , H01L21/762
CPC分类号： H01L27/0928 , H01L21/26513 , H01L21/76224 , H01L21/823892 , H01L27/10897 , H01L29/0688 , H01L29/1095 , H01L29/36
摘要： Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

57. 发明授权

US09269812B2 Semiconductor device having V-shaped region 有权
标题翻译：具有V形区域的半导体器件
公开(公告)号：US09269812B2
公开(公告)日：2016-02-23
申请号：US14600095
申请日：2015-01-20
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L29/78 , H01L21/36 , H01L21/8238 , H01L29/66 , H01L29/06 , H01L29/165 , H01L27/092 , H01L29/10 , H01L29/161
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L27/0928 , H01L29/06 , H01L29/1058 , H01L29/1079 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.
摘要翻译：其中，本文提供半导体器件或晶体管以及用于形成半导体器件的方法。半导体器件包括一个或多个V形凹槽，其中生长诸如硅锗的应力单晶半导体材料，以形成半导体器件的源极或漏极中的至少一个。一个或多个V形凹槽原位蚀刻到基底中。当半导体器件（例如，第一晶体管）的第一部分和半导体器件的第二部分（例如，第一晶体管）之间的多晶间隔时，半导体器件包括高度与长度之比超过至少1.6的源极或漏极中的至少一个（例如，第二晶体管）小于约60nm。

58. 发明授权

US09251865B2 Selective coupling of voltage feeds for body bias voltage in an integrated circuit device 有权
公开(公告)号：US09251865B2
公开(公告)日：2016-02-02
申请号：US12069670
申请日：2008-02-11
申请人： James B. Burr , Robert Fu
发明人： James B. Burr , Robert Fu
IPC分类号： H01L27/108 , H01L23/62 , G11C5/14 , H01L21/8234 , H01L21/8238 , H01L27/02 , H01L27/092
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

59. 发明授权

US09240412B2 Semiconductor structure and device and methods of forming same using selective epitaxial process 有权
标题翻译：使用选择性外延工艺的半导体结构及其形成方法
公开(公告)号：US09240412B2
公开(公告)日：2016-01-19
申请号：US14040196
申请日：2013-09-27
申请人： ASM IP Holding B.V.
发明人： Qi Xie , Vladimir Machkaoutsan , Jan Willem Maes
IPC分类号： H01L21/336 , H01L27/092 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/823821 , H01L27/0928 , H01L29/0649 , H01L29/165
摘要： Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.
摘要翻译：公开了形成结构和装置的半导体结构，器件和方法。示例性结构包括可以包括再通道MOS（NMOS）和p沟道MOS（PMOS）器件的多栅极或FinFET结构，以在衬底上形成CMOS结构和器件。可以使用选择性外延和浅沟槽隔离技术来形成器件。

60. 发明申请

US20150380413A1 COMPACT CMOS DEVICE ISOLATION 有权
标题翻译：紧凑的CMOS器件隔离
公开(公告)号：US20150380413A1
公开(公告)日：2015-12-31
申请号：US14320451
申请日：2014-06-30
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L27/092 , H01L29/06 , H01L21/8238
CPC分类号： H01L29/0646 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0928 , H01L29/1083
摘要： An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and overlapping at least partially the second well encircling the first well. In an alternate embodiment, instead of the buried layer, the integrated circuit includes a third well of the second conductivity type formed in the semiconductor layer where the third well contains the first well and overlaps at least partially the second well encircling the first well.
摘要翻译：集成电路包括形成在半导体层中的第一导电类型的第一阱，其中第一阱容纳有源器件并连接到第一阱电位，形成在半导体层中的第二导电类型的第二阱并且环绕第一阱电位其中第二阱壳体有源器件并连接到第二阱电位，以及形成在第一阱下面并且至少部分地覆盖环绕第一阱的第二阱的第二导电类型的掩埋层。在替代实施例中，代替埋层，集成电路包括形成在半导体层中的第二导电类型的第三阱，其中第三阱包含第一阱并且至少部分地重叠包围第一阱的第二阱。

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