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51. 发明授权

US09350334B2 Nonvolatile latch circuit and logic circuit, and semiconductor device using the same 有权
公开(公告)号：US09350334B2
公开(公告)日：2016-05-24
申请号：US14510310
申请日：2014-10-09
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kiyoshi Kato , Jun Koyama
IPC分类号： H03K3/00 , H03K3/356 , G11C7/04 , G11C14/00 , H01L27/105 , H01L27/12 , H03K3/037 , H03K3/286 , G11C16/04 , H01L21/02 , H01L21/28 , H01L29/66
CPC分类号： H03K3/356104 , G11C7/04 , G11C14/0063 , G11C16/045 , G11C2211/4016 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/28202 , H01L21/28211 , H01L27/105 , H01L27/1203 , H01L27/1225 , H01L29/6659 , H03K3/0375 , H03K3/286 , H03K3/356 , H03K3/356121 , H03K3/356173
摘要： To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

52. 发明授权

US09318196B1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09318196B1
公开(公告)日：2016-04-19
申请号：US14725740
申请日：2015-05-29
申请人： Floadia Corporation
发明人： Hideo Kasai , Yutaka Shinagawa , Ryotaro Sakurai , Yasuhiro Taniguchi , Kosuke Okuyama
IPC分类号： G11C16/04 , G11C14/00 , G11C11/417 , H01L29/423 , G11C11/419 , G11C16/24
CPC分类号： G11C14/0063 , G11C5/025 , G11C11/417 , G11C11/419 , G11C16/10
摘要： In a non-volatile semiconductor memory device capable of programming SRAM data in an SRAM into a non-volatile memory unit while implementing a high-speed operation in the SRAM, a voltage required to program the SRAM data into the non-volatile memory unit can be lowered. Thus, the SRAM can be operated at high speed with a low power supply voltage because the thickness of a gate insulating film of each of a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor constituting the SRAM connected to the non-volatile memory unit can be set to 4 [nm] or less. Therefore, the SRAM data in the SRAM can be programmed into the non-volatile memory unit while a high-speed operation in the SRAM can be implemented.
摘要翻译：在能够将SRAM中的SRAM数据编程成非易失性存储器单元同时在SRAM中实现高速操作的非易失性半导体存储器件中，将SRAM数据编程到非易失性存储器单元中所需的电压可以被降低因此，由于第一存取晶体管，第二存取晶体管，第一负载晶体管，第二负载晶体管，第一驱动器中的每一个的栅极绝缘膜的厚度，SRAM可以以较低的电源电压高速运行晶体管和构成连接到非易失性存储单元的SRAM的第二驱动晶体管可以被设置为4 [nm]或更小。因此，可以将SRAM中的SRAM数据编程到非易失性存储器单元中，同时可以实现SRAM中的高速操作。

53. 发明申请

US20160078938A1 METHOD AND APPARATUS FOR PROVIDING MULTI-PAGE READ AND WRITE USING SRAM AND NONVOLATILE MEMORY DEVICES 有权
标题翻译：使用SRAM和非易失性存储器件提供多页读取和写入的方法和装置
公开(公告)号：US20160078938A1
公开(公告)日：2016-03-17
申请号：US14855323
申请日：2015-09-15
申请人： NEO Semiconductor, Inc.
发明人： Fu-Chang Hsu
IPC分类号： G11C14/00 , G11C16/04 , G11C11/419 , G11C16/10
CPC分类号： G11C14/0063 , G11C11/005 , G11C11/419 , G11C16/0483 , G11C16/10
摘要： A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.
摘要翻译：存储器件包括静态随机存取存储器（“SRAM”）电路和第一非易失性存储器（“NVM”）串，第二NVM串，第一和第二漏极选择栅极（“DSG”）。 SRAM电路能够临时存储响应于在SRAM电路的输入端耦合的位线（“BL”）信息的信息。具有至少一个非易失性存储单元的第一NVM串耦合到SRAM的输出端。第一DSG可操作以控制在SRAM的输出端处将信息存储到第一非易失性存储器的定时。具有至少一个非易失性存储单元的第二NVM串耦合到SRAM的输出端。第二DSG控制用于将SRAM的输出端子处的信息存储到第二非易失性存储器串的定时。

54. 发明申请

US20150325299A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF 有权
标题翻译：非挥发性半导体存储器件及其写入方法
公开(公告)号：US20150325299A1
公开(公告)日：2015-11-12
申请号：US14625436
申请日：2015-02-18
申请人： POWERCHIP TECHNOLOGY CORPORATION
发明人： Mathias Yves Gilbert BAYLE
IPC分类号： G11C16/10 , G11C16/34 , G11C14/00
CPC分类号： G11C16/10 , G11C8/08 , G11C8/10 , G11C8/14 , G11C14/0063 , G11C16/0483 , G11C16/08 , G11C16/3427
摘要： A non-volatile semiconductor memory device utilized to implement the writing of data by adding a predetermined voltage for assigning a word line to a non-volatile memory cell includes a control process or generating and outputting control data implementing a program code for writing data including a word line assignment command and voltage source assignment data, a writing controller decoding the control data and generating a control signal of the word line assignment command and a control signal of the voltage source assignment data, a voltage generation circuit generating several voltages for writing data, and a switch circuit selecting a voltage, corresponding to voltage source assignment data, among several voltages, according to the control signal of the word line assignment command and the control signal of voltage source assignment data and outputting the selected voltage to the word line corresponding to the word line assignment command.
摘要翻译：用于通过添加用于将字线分配给非易失性存储单元的预定电压来实现数据写入的非易失性半导体存储器件包括控制处理或产生和输出实现用于写入数据的程序代码的控制数据，所述程序代码包括字线分配命令和电压源分配数据，写入控制器对控制数据进行解码并产生字线分配命令的控制信号和电压源分配数据的控制信号，产生用于写数据的多个电压的电压产生电路，以及开关电路，根据字线分配指令的控制信号和电压源分配数据的控制信号，在多个电压中选择与电压源分配数据对应的电压，并将选择的电压输出到对应于字线分配命令。

55. 发明申请

US20150269989A1 Semiconductor Structure and Memory Device including the Structure 有权
标题翻译：包括结构的半导体结构和存储器件
公开(公告)号：US20150269989A1
公开(公告)日：2015-09-24
申请号：US14657914
申请日：2015-03-13
申请人： STMicroelectronics (Rousset) SAS
发明人： François Tailliet , Marc Battista
IPC分类号： G11C11/41 , H01L27/11 , G11C14/00 , G11C16/04
CPC分类号： G11C11/41 , G11C11/4125 , G11C14/0054 , G11C14/0063 , G11C16/0416 , H01L23/5226 , H01L27/1104 , H01L29/0847 , H01L29/42364 , H01L29/513 , H01L29/518 , H01L29/788
摘要： A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
摘要翻译：半导体结构包括设置在半导体本体中并通过沟道区彼此隔开的第一和第二源/漏区。栅电极覆盖沟道区域，电容器电极设置在栅电极和沟道区之间。第一栅极电介质设置在栅电极和电容器电极之间，第二栅极电介质设置在电容器电极和沟道区之间。第一导电接触区域与栅电极电接触，以及与电容器电极电接触的第二导电接触区域。第一和第二接触区域彼此电隔离。

56. 发明授权

US09142261B2 Smart bridge for memory core 有权
标题翻译：内存核心智能桥
公开(公告)号：US09142261B2
公开(公告)日：2015-09-22
申请号：US14246548
申请日：2014-04-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Manuel Antonio D'Abreu , Stephen Skala , Dimitris Pantelakis , Radhakrishnan Nair , Deepak Pancholi
IPC分类号： G11C7/00 , G11C5/02 , G06F13/16 , G06F11/10 , G11C14/00 , G11C16/10 , G11C16/26 , G11C29/04
CPC分类号： G11C5/02 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G06F13/1668 , G11C14/0063 , G11C16/10 , G11C16/26 , G11C29/04 , G11C2029/0411 , Y02D10/14
摘要： An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.
摘要翻译：一种装置包括包括三维（3D）存储器的半导体器件。 3D存储器包括布置在衬底上方多个物理层的多个存储单元。 3D存储器包括与多个存储器单元的操作相关联的电路并且包括串行器/解串器接口。

57. 发明授权

US09123413B2 Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device 有权
标题翻译：用于管理具有SRAM存储器平面和非易失性存储器平面的存储器件的操作的方法以及相应的存储器件
公开(公告)号：US09123413B2
公开(公告)日：2015-09-01
申请号：US14315401
申请日：2014-06-26
申请人： STMicroelectronics (Rousset) SAS
发明人： François Tailliet , Marc Battista
IPC分类号： G11C11/34 , G11C14/00 , G11C7/10 , G11C16/04 , G11C16/34
CPC分类号： G11C14/0063 , G11C7/1006 , G11C16/0408 , G11C16/3418
摘要： A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.
摘要翻译：一种方法可用于管理包括彼此耦合的SRAM基本存储单元和非易失性基本存储单元的存储单元的操作。数据位在SRAM单元存储单元和非易失性单元存储单元之间传送。控制数据被存储在功能上类似于存储器单元并与其相关联的控制存储器单元中。从SRAM基本存储单元读取数据位，并执行相应的控制数据读取。如果控制数据具有第一值，则从SRAM基本存储器单元读取的数据位被反转，但是如果控制数据具有第二值，则从SRAM基本存储单元读取的数据位不反转。

58. 发明授权

US09001583B2 On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation 有权
标题翻译：作为NVSRAM自动存储操作的第二个备用电源的片上HV和LV电容
公开(公告)号：US09001583B2
公开(公告)日：2015-04-07
申请号：US14053549
申请日：2013-10-14
申请人： Aplus Flash Technology, Inc
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C11/34 , G11C16/30 , G11C5/14 , G11C14/00 , G11C16/12 , G11C16/22
CPC分类号： G11C16/30 , G11C5/141 , G11C14/0063 , G11C16/12 , G11C16/22
摘要： Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM's Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.
摘要翻译：两个片上电容器包括一个HV电容器VPPcap和一个LV VCC电容器VCCcap，构成NVSRAM存储器芯片，作为每个NVSRAM单元的备用第二个电源，无论1-poly，2-poly，PMOS或NMOS闪存其中的细胞结构。片上HV和LV电容器优选地由用于实现所需电容的一个或多个MIM或MIP层制成。提出了一种简化的VCC电源系统电路，不需要设计用于仅执行一个NVSRAM编程操作而不进行擦除操作的状态机，用于启动NVSRAM的自动存储操作，而不使用任何片外Vbat和Vcap。在自动存储操作期间，一旦VCC检测器检测到VCC电压降低到正常VDD电平的80％，则与两个片上电容器相关的所有HV泵和振荡器都将被关闭。

59. 发明申请

US20140313827A1 MEMORY CIRCUIT 有权
标题翻译：存储器电路
公开(公告)号：US20140313827A1
公开(公告)日：2014-10-23
申请号：US14318841
申请日：2014-06-30
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takuro Ohmaru
IPC分类号： G11C14/00
CPC分类号： G11C14/0018 , G11C5/14 , G11C11/34 , G11C11/41 , G11C14/00 , G11C14/0063 , H01L21/8258 , H01L27/0688 , H01L27/1156 , H01L27/1207 , H01L29/788 , H01L29/792
摘要： The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.
摘要翻译：本发明提供了一种存储电路，其中在不提供电力的情况下，已经保存在与易失性存储器相对应的存储器部分中的数据信号可以被保存在与非易失性存储器相对应的存储器部分中的电容器中。在非易失性存储器部分中，其沟道形成在氧化物半导体层中的晶体管允许信号被长时间保持在电容器中。因此，即使在电源停止的情况下，存储电路也可以保持逻辑状态（数据信号）。施加到其沟道形成在氧化物半导体层中的晶体管的栅极的电位由设置在用于承载电源电位的布线和晶体管的栅极之间的升压电路升高，允许数据信号被保持为一个电源电位无故障。

60. 发明授权

US08837219B2 Method of programming nonvolatile memory 有权
标题翻译：非易失性存储器编程方法
公开(公告)号：US08837219B2
公开(公告)日：2014-09-16
申请号：US13468043
申请日：2012-05-10
申请人： Kai-Yuan Hsiao , Wen-Yuan Lee , Yun-Jen Ting , Cheng-Jye Liu , Wein-Town Sun
发明人： Kai-Yuan Hsiao , Wen-Yuan Lee , Yun-Jen Ting , Cheng-Jye Liu , Wein-Town Sun
IPC分类号： G11C16/04 , G11C14/00 , H01L27/115 , H01L29/792
CPC分类号： G11C16/0466 , G11C14/00 , G11C14/0063 , G11C16/0416 , H01L27/11565 , H01L29/792
摘要： Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.
摘要翻译：存储器的多个存储单元的每个存储单元具有阱，源极和漏极区，存储层和栅极。存储单元是矩阵。相同的列漏极区域连接到相同的位线，相同的行栅极连接到相同的字线，并且相同的列源区域连接到相同的源极线。通过将第一电压施加到电连接到多个存储器单元的存储单元的字线来对存储器进行编程，将不同于第一电压的第二电压施加至少编程阈值至与存储器电连接的位线将与所述第一电压不同的第三电压施加至所述编程阈值至与所述存储单元电连接的源极线，以及向所述多个存储单元施加衬底电压。

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