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51. 发明申请

US20180113969A1 HETEROGENEOUS MINIATURIZATION PLATFORM 审中-公开
公开(公告)号：US20180113969A1
公开(公告)日：2018-04-26
申请号：US15626582
申请日：2017-06-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qianwen Chen , Li-Wen Hung , Wanki Kim , John U. Knickerbocker , Kenneth P. Rodbell , Robert L. Wisnieff
IPC分类号： G06F17/50 , G06F15/78
CPC分类号： G06F17/5027 , G06F15/7803 , G06F15/7807 , G06F15/7857 , G06F15/803 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L24/17 , H01L25/065 , H01L25/0655 , H01L25/071 , H01L25/112 , H01L25/115 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68368 , H01L2221/68381 , H01L2224/08225 , H01L2224/11002 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/80006 , H01L2224/81005 , H01L2924/1205 , H01L2924/1206 , H01L2924/13051 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/1432 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
摘要： A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

52. 发明申请

US20140208033A1 Split-Word Memory 有权
标题翻译：分割字记忆
公开(公告)号：US20140208033A1
公开(公告)日：2014-07-24
申请号：US14221661
申请日：2014-03-21
申请人： Lutz Naethke , Axel Borkowski , Bert Bretschneider , Kyriakos A. Stavrou , Rainer Theuer
发明人： Lutz Naethke , Axel Borkowski , Bert Bretschneider , Kyriakos A. Stavrou , Rainer Theuer
IPC分类号： G06F12/08
CPC分类号： G06F9/3802 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30185 , G06F9/30192 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3887 , G06F9/3889 , G06F12/00 , G06F12/04 , G06F12/0607 , G06F12/0846 , G06F12/0862 , G06F12/0875 , G06F15/7807 , G06F15/7857 , G06F2212/452 , G06F2212/6028 , Y02D10/12 , Y02D10/13
摘要： Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.
摘要翻译：有效地存储，读取和/或处理单词数据音节的方法，过程和装置。包括多个音节的数据字的一部分可以被计算机处理器读取。处理器可以从第一存储器读取数据字的第一个音节。处理器可以从存储器的第二部分读取数据字的第二个音节。第二个音节可以包括比第一个音节的位不太关键的比特。第二存储器可以基于一个或多个物理属性与第一存储器不同。

53. 发明申请

US20110113115A1 STORAGE SYSTEM WITH A MEMORY BLADE THAT GENERATES A COMPUTATIONAL RESULT FOR A STORAGE DEVICE 有权
标题翻译：具有生成存储设备的计算结果的存储器的存储系统
公开(公告)号：US20110113115A1
公开(公告)日：2011-05-12
申请号：US12613537
申请日：2009-11-06
申请人： Jichuan Chang , Kevin T. Lim , Parthasarathy Ranganathan
发明人： Jichuan Chang , Kevin T. Lim , Parthasarathy Ranganathan
IPC分类号： G06F15/167 , G06F12/00 , G06F15/173
CPC分类号： G06F15/7803 , G06F15/7857 , G06F15/786
摘要： One embodiment is a storage system having one or more compute blades to generate and use data and one or more memory blades to generate a computational result. The computational result is generated by a computational function that transforms the data generated and used by the one or more compute blades. One or more storage devices are in communication with and remotely located from the one or more compute blades. The one or more storage devices store and serve the data for the one or more compute blades.
摘要翻译：一个实施例是具有一个或多个计算刀片以产生和使用数据的存储系统以及一个或多个存储器刀片以产生计算结果。计算结果由计算功能产生，该计算函数转换由一个或多个计算刀片生成和使用的数据。一个或多个存储设备与一个或多个计算刀片通信并远程定位于一个或多个计算刀片。一个或多个存储设备存储和服务于一个或多个计算刀片的数据。

54. 发明申请

US20090254718A1 Local Memories with Permutation Functionality for Digital Signal Processors 有权
标题翻译：具有数字信号处理器置换功能的本地存储器
公开(公告)号：US20090254718A1
公开(公告)日：2009-10-08
申请号：US12399719
申请日：2009-03-06
申请人： Eric Biscondi , David J. Hoyle , Tod D. Wolf
发明人： Eric Biscondi , David J. Hoyle , Tod D. Wolf
IPC分类号： G06F15/76 , G06F12/06 , G06F12/00 , G06F9/02
CPC分类号： G06F15/7857 , G06F9/30018 , G06F9/30032 , G06F9/3885
摘要： A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.
摘要翻译：根据具有本地存储器的集群架构的数字信号处理器（DSP）协处理器。架构中的每个集群包括多个子集群，每个子集群能够执行一个或两个指令，这些指令可以专门针对特定的DSP操作。每个集群中的子集群通过集群中的交叉开关与全局内存资源进行通信。子集群中的一个或多个具有专用本地存储器，其可以以随机存取方式，向量存取方式或以流或堆栈方式访问。本地存储器被布置为多个存储体。响应于某些向量访问指令，可以根据存储在寄存器中的置换模式，在写入之前在存储体之间排列输入数据，或者在从存储体读取之后被置换。

55. 发明授权

US07533196B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07533196B2
公开(公告)日：2009-05-12
申请号：US11589840
申请日：2006-10-31
申请人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
发明人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
IPC分类号： G06F13/28
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译：半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

56. 发明授权

US07395298B2 Method and apparatus for performing multiply-add operations on packed data 失效
标题翻译：对打包数据执行多重加法运算的方法和装置
公开(公告)号：US07395298B2
公开(公告)日：2008-07-01
申请号：US10611621
申请日：2003-06-30
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler , Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler , Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , G06F7/4812 , G06F7/49921 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F15/7857 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

57. 发明授权

US07315918B1 Processor block placement relative to memory in a programmable logic device 有权
标题翻译：相对于可编程逻辑器件中的存储器的处理器块放置
公开(公告)号：US07315918B1
公开(公告)日：2008-01-01
申请号：US11035776
申请日：2005-01-14
申请人： Robert Yin
发明人： Robert Yin
IPC分类号： G06F12/00
CPC分类号： G06F15/7857
摘要： A programmable logic device having groups of data and instruction memory blocks separated by a processor block is described. The processor block including an embedded processor and data and instruction memory controllers. The data and instruction memory blocks respectively including data and memory groupings of block random access memories.
摘要翻译：描述了具有由处理器块分隔的数据组和指令存储器块的可编程逻辑器件。处理器块包括嵌入式处理器和数据和指令存储器控制器。数据和指令存储器块分别包括块随机存取存储器的数据和存储器分组。

58. 发明授权

US06704023B1 3-D graphics chip with embedded DRAMbuffers 有权
标题翻译：具有嵌入式DRAM缓冲器的3-D图形芯片
公开(公告)号：US06704023B1
公开(公告)日：2004-03-09
申请号：US10341852
申请日：2003-01-13
申请人： Tsailai Terry Wu , Yudianto Halim
发明人： Tsailai Terry Wu , Yudianto Halim
IPC分类号： G09G536
CPC分类号： G06F9/5016 , G06F9/3879 , G06F15/7857
摘要： A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.
摘要翻译： 3-D图形芯片包括独立的内部DRAM缓冲器，每个缓冲器具有用于连接到3-D纹理渲染绘图引擎的宽带宽存取总线。 3-D绘图引擎利用灵活的嵌入式存储器接口来将传统的3-D流水线延迟降低3倍。在具体实施例中，三个绘制过程中的每一个 - 纹理，Z，像素 - 检索和存储信息在单独的嵌入式绘图缓冲区中通过单独的宽带宽访问总线。通过单独的外部访问总线提供对外部存储器的访问。在另一个具体实施例中，3-D绘图引擎通过读写FIFO访问嵌入式绘图缓冲器，以最大化绘制过程的吞吐量。

59. 发明授权

US06510510B1 Digital signal processor having distributed register file 有权
标题翻译：具有分布式寄存器文件的数字信号处理器
公开(公告)号：US06510510B1
公开(公告)日：2003-01-21
申请号：US09218346
申请日：1998-12-22
申请人： Douglas Garde
发明人： Douglas Garde
IPC分类号： G06F1500
CPC分类号： G06F9/3824 , G06F9/30036 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/382 , G06F9/383 , G06F9/3861 , G06F9/3885 , G06F15/7857 , Y02D10/13
摘要： A computation block for use in a digital signal processor includes a register file for storage of operands and results and one or more computation units for executing digital signal computations. A first digital signal computation is performed with one of the computation units, and an intermediate result is produced. The intermediate result is transferred from a result output of the computation unit to an intermediate result input of one or more of the computation units without first transferring the intermediate result to the register file. A second digital signal computation is performed using the intermediate result to produce a final result or a second intermediate result.
摘要翻译：用于数字信号处理器的计算块包括用于存储操作数和结果的寄存器文件以及用于执行数字信号计算的一个或多个计算单元。使用计算单元之一执行第一数字信号计算，并产生中间结果。中间结果从计算单元的结果输出传送到一个或多个计算单元的中间结果输入，而不先将中间结果传送到寄存器文件。使用中间结果执行第二数字信号计算以产生最终结果或第二中间结果。

60. 发明授权

US06496920B1 Digital signal processor having multiple access registers 失效
标题翻译：具有多个存取寄存器的数字信号处理器
公开(公告)号：US06496920B1
公开(公告)日：2002-12-17
申请号：US09044088
申请日：1998-03-18
申请人： Qiuzhen Zou , Gilbert C. Sih , Jian Lin
发明人： Qiuzhen Zou , Gilbert C. Sih , Jian Lin
IPC分类号： G06F900
CPC分类号： G06F9/30109 , G06F9/30014 , G06F9/30032 , G06F9/30043 , G06F9/30141 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3826 , G06F9/3853 , G06F9/3885 , G06F9/3893 , G06F12/04 , G06F15/7857
摘要： A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory is separate from the set of three data memories.
摘要翻译：一种用于数字信号处理的方法和电路。所公开的方法和电路使用可变长度指令集。可变长度指令的一部分可以存储在存储器内的相邻位置。指令的开始和结束可能跨越存储器字边界发生。指令可能包含导致执行特定操作的可变数目的指令片段。所公开的电路具有一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。数据总线包括一条宽公共汽车和两条窄车。宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。此外，所公开的电路具有可由至少两个处理单元访问的寄存器组。所公开的电路还包括指令提取单元，其接收存储在指令存储器中的可变长度的指令。指令存储器与三组数据存储器分开。

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