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    • 51. 发明授权
    • Interleaver using spatial birefringent elements
    • 交织器使用空间双折射元件
    • US06781754B2
    • 2004-08-24
    • US09876368
    • 2001-06-07
    • Bin Zhao
    • Bin Zhao
    • G02B530
    • G02B27/283
    • An interleaver has an input polarization beam displacer, a birefringent filter assembly in optical communication with the input polarization beam displacer, a first output polarization beam displacer in optical communication with the birefringent filter assembly and a second output polarization beam displacer optical communication with the first output polarization beam displacer. The birefringent filter assembly preferably comprises at least one birefringent filter stage, wherein each birefringent filter stage comprises a first filter polarization beam displacer, a second filter polarization beam displacer and at least one reflector configured so as to direct light from first filter polarization beam displacer to the second filter of polarization beam displacer.
    • 交织器具有输入偏振光束置换器,与输入偏振光束置换器光学通信的双折射滤光器组件,与双折射滤光器组件光学通信的第一输出偏振光束置换器和与第一输出光学通信的第二输出偏振光束置换器 偏振光束置换器。 双折射滤光器组件优选地包括至少一个双折射滤光器级,其中每个双折射滤光镜级包括第一滤光器偏振光束置换器,第二滤光器偏振光束置换器和至少一个反射器,其被配置为将来自第一滤光器偏振光束置换器的光引导到 偏振光束置换器的第二滤光器。
    • 52. 发明授权
    • Method of forming dual-damascene interconnect structures employing low-k dielectric materials
    • 使用低k电介质材料形成双镶嵌互连结构的方法
    • US06627539B1
    • 2003-09-30
    • US09149910
    • 1998-09-09
    • Bin ZhaoMaureen R. Brongo
    • Bin ZhaoMaureen R. Brongo
    • H01L2144
    • H01L23/5329H01L21/76807H01L2924/0002H01L2924/00
    • Interconnects in sub-micron and sub-half-micron integrated circuit devices are fabricated using a dual damascene process incorporating a low-k dielectric. A dual-damascene structure can be implemented without the necessity of building a single damascene base, and without CMP of the low-k dielectric. This structure simplifies the manufacturing process, reduces cost, and effectively reduces intra-level and inter-level capacitance, resistivity, and noise related to substrate coupling. In accordance with a further aspect of the present invention, a modified silicon oxide material such as silsesquioxane is used for the low-k dielectric in conjunction with silicon dioxide cap layers, allowing an improved process window and simplifying the etching process.
    • 使用包含低k电介质的双镶嵌工艺制造亚微米和亚半微米集成电路器件中的互连。 可以实现双镶嵌结构,而不需要构建单个镶嵌基底,并且不需要低k电介质的CMP。 该结构简化了制造工艺,降低了成本,并且有效地降低了与衬底耦合有关的电平,电平和电平以及噪声。 根据本发明的另一方面,与二氧化硅盖层结合使用改性氧化硅材料如倍半硅氧烷用于低k电介质,允许改进的工艺窗口并简化蚀刻工艺。
    • 54. 发明授权
    • Method of making a damascene metallization
    • 制作镶嵌金属化的方法
    • US5736457A
    • 1998-04-07
    • US811954
    • 1997-03-05
    • Bin Zhao
    • Bin Zhao
    • H01L21/768H01L21/4763
    • H01L21/7681H01L21/76807H01L21/7684H01L2221/1036
    • A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectrics in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.
    • 提供半导体工艺和结构用于单镶嵌金属化或双镶嵌金属化工艺。 用作蚀刻停止和掩蔽层的薄金属层沉积在第一介电层上。 然后,在薄金属化掩模层上沉积第二介电层。 薄金属化掩模层提供蚀刻停止以形成嵌入式导体槽的底部。 在双镶嵌工艺中,薄的金属化掩模层离开通孔区域。 因此,可以在一个步骤中在金属化屏蔽层上方的导体沟槽和通孔区域在第一和第二电介质中被蚀刻。 在单个镶嵌工艺中,薄金属化蚀刻掩模层可以覆盖通孔区域。 蚀刻停止和掩蔽层可以由其化学,机械,热和电特性与工艺和电路性能兼容的任何导电或非导电材料形成。