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51. 发明申请

US20100164521A1 Parametric Testline with Increased Test Pattern Areas 有权
标题翻译：参数测试线与增加的测试模式区域
公开(公告)号：US20100164521A1
公开(公告)日：2010-07-01
申请号：US12704252
申请日：2010-02-11
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
摘要翻译：公开了一种提供增加的测试图案区域的集成电路参数测试线。测试线包括衬底上的电介质层，电介质层上的多个探针焊盘，以及形成在探针焊盘下方空间中的测试线中的第一被测器件（DUT）。测试线还可以包括第二DUT，其以覆盖配置形成在覆盖第一DUT的探针焊盘下方的空间中。测试线还可以包括多边形形状的探针焊盘结构，其提供相邻探针焊盘之间增加的测试图案区域。

52. 发明申请

US20090081862A1 AIR GAP STRUCTURE DESIGN FOR ADVANCED INTEGRATED CIRCUIT TECHNOLOGY 审中-公开
标题翻译：高级集成电路技术的空气隙结构设计
公开(公告)号：US20090081862A1
公开(公告)日：2009-03-26
申请号：US11860122
申请日：2007-09-24
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Benson Liu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Benson Liu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76831
摘要： A method for forming air gaps between interconnect structures in semiconductor devices provides a sacrificial layer formed over a dielectric and within openings formed therein. The sacrificial layer is a blanket layer that is converted to a material that is consumable in an etchant composition that the dielectric material and a subsequently formed interconnect material are resistant to. After the interconnect material is deposited a planarized surface including portions of the dielectric material, vertical sections of the converted material and portions of the interconnect material is produced. The etchant composition then removes the converted material thereby forming voids. A capping layer is formed over the structure resulting in air gaps. A sidewall protection layer may be optionally formed between the interconnect structure and the sacrificial material. In some embodiments an ARC layer may be formed over the dielectric and form part of the planar surface.
摘要翻译：用于在半导体器件中的互连结构之间形成气隙的方法提供了形成在电介质上并在其内形成的开口内的牺牲层。牺牲层是覆盖层，其被转化为在蚀刻剂组合物中消耗的材料，电介质材料和随后形成的互连材料是耐受的。在互连材料沉积之后，包括介电材料的部分的平坦化表面，产生转换材料的垂直部分和互连材料的部分。然后蚀刻剂组合物去除转化的材料，从而形成空隙。在结构上形成覆盖层，导致气隙。侧壁保护层可以可选地形成在互连结构和牺牲材料之间。在一些实施例中，可以在电介质上形成ARC层并形成平面表面的一部分。

53. 发明申请

US20080217735A1 Metal e-Fuse structure design 有权
标题翻译：金属电子保险丝结构设计
公开(公告)号：US20080217735A1
公开(公告)日：2008-09-11
申请号：US11716206
申请日：2007-03-09
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Shih-Hsun Hsu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.
摘要翻译：提供集成电路结构。集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的金属保险丝; 与金属保险丝相邻的虚拟图案; 以及介电层中的金属线，其中金属熔丝的厚度基本上小于金属线的厚度。

54. 发明申请

US20070015365A1 Method and apparatus for enhanced CMP planarization using surrounded dummy design 有权
公开(公告)号：US20070015365A1
公开(公告)日：2007-01-18
申请号：US11181433
申请日：2005-07-14
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/31053
摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

55. 发明授权

US08125233B2 Parametric testline with increased test pattern areas 有权
标题翻译：参数测试线具有增加的测试图案区域
公开(公告)号：US08125233B2
公开(公告)日：2012-02-28
申请号：US12704252
申请日：2010-02-11
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
摘要翻译：公开了一种提供增加的测试图案区域的集成电路参数测试线。测试线包括衬底上的电介质层，电介质层上的多个探针焊盘，以及形成在探针焊盘下方空间中的测试线中的第一被测器件（DUT）。测试线还可以包括第二DUT，其以覆盖配置形成在覆盖第一DUT的探针焊盘下方的空间中。测试线还可以包括多边形形状的探针焊盘结构，其提供相邻探针焊盘之间增加的测试图案区域。

56. 发明申请

US20110062597A1 PACKAGE STRUCTURES 有权
标题翻译：包装结构
公开(公告)号：US20110062597A1
公开(公告)日：2011-03-17
申请号：US12946930
申请日：2010-11-16
申请人： Benson LIU , Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
发明人： Benson LIU , Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L25/07
CPC分类号： H01L25/0657 , H01L2224/16225 , H01L2224/48227 , H01L2225/06555 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
摘要翻译：封装结构包括衬底，第一管芯和至少一个第二管芯。衬底包括第一对平行边缘和第二对平行边缘。第一个模具安装在基板上。第一管芯包括第三对平行边缘和第四对平行边缘，其中第三对平行边缘和第四对平行边缘不平行于第一对平行边缘和第二对平行边缘，分别。至少一个第二管芯安装在第一管芯上。

57. 发明申请

US20090298256A1 SEMICONDUCTOR INTERCONNECT AIR GAP FORMATION PROCESS 失效
公开(公告)号：US20090298256A1
公开(公告)日：2009-12-03
申请号：US12132233
申请日：2008-06-03
申请人： Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
发明人： Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/76
CPC分类号： H01L21/7682
摘要： A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided.
摘要翻译：一种包括互连气隙的半导体封装及其制造方法。半导体封装包括电介质层，金属互连，设置在电介质层和互连之间的空气间隙和散布在金属互连和气隙之间的间隔物。金属互连由间隔件横向支撑并与气隙隔离。还提供了制造该方法的方法。

58. 发明授权

US08749020B2 Metal e-fuse structure design 有权
标题翻译：金属电熔丝结构设计
公开(公告)号：US08749020B2
公开(公告)日：2014-06-10
申请号：US11716206
申请日：2007-03-09
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Shih-Hsun Hsu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.
摘要翻译：提供集成电路结构。集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的金属保险丝; 与金属保险丝相邻的虚拟图案; 以及介电层中的金属线，其中金属熔丝的厚度基本上小于金属线的厚度。

59. 发明授权

US08618673B2 Package structures 有权
标题翻译：包装结构
公开(公告)号：US08618673B2
公开(公告)日：2013-12-31
申请号：US13539775
申请日：2012-07-02
申请人： Benson Liu , Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
发明人： Benson Liu , Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L25/0657 , H01L2224/16225 , H01L2224/48227 , H01L2225/06555 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
摘要翻译：封装结构包括衬底，第一管芯和至少一个第二管芯。衬底包括第一对平行边缘和第二对平行边缘。第一个模具安装在基板上。第一管芯包括第三对平行边缘和第四对平行边缘，其中第三对平行边缘和第四对平行边缘不平行于第一对平行边缘和第二对平行边缘，分别。至少一个第二管芯安装在第一管芯上。

60. 发明授权

US07679384B2 Parametric testline with increased test pattern areas 有权
标题翻译：参数测试线具有增加的测试图案区域
公开(公告)号：US07679384B2
公开(公告)日：2010-03-16
申请号：US11811135
申请日：2007-06-08
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
摘要翻译：公开了一种提供增加的测试图案区域的集成电路参数测试线。测试线包括衬底上的电介质层，电介质层上的多个探针焊盘，以及形成在探针焊盘下方空间中的测试线中的第一被测器件（DUT）。测试线还可以包括第二DUT，其以覆盖配置形成在覆盖第一DUT的探针焊盘下方的空间中。测试线还可以包括多边形形状的探针焊盘结构，其提供相邻探针焊盘之间增加的测试图案区域。

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