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    • 52. 发明申请
    • Phase Locked Loop and 3-Stage Frequency Divider
    • 锁相环和三级分频器
    • US20110018596A1
    • 2011-01-27
    • US12898360
    • 2010-10-05
    • Jri LeeMing-Chung Liu
    • Jri LeeMing-Chung Liu
    • H03L7/08H03K23/00
    • H03L7/113H03L7/085H03L7/099H03L7/18H03L7/191
    • The phase locked loop has a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The 3-stage frequency divider comprises three cascaded frequency dividers with different rangers of operating frequencies.
    • 锁相环具有相位检波器(PFD),环路滤波器(LF),压控振荡器(VCO)和三级分频器。 PFD接收参考信号和反馈信号以确定相位和频率误差。 耦合到相位频率检测器的LF)对相位和频率误差进行滤波以产生控制电压。 耦合到环路滤波器的VCO根据控制电压产生VCO输出信号。 耦合到压控振荡器的3级分频器将VCO输出信号的频率分频3次以产生反馈信号。 三级分频器包括三个级联分频器,具有不同的工作频率范围。