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51. 发明申请

US20060232310A1 System and method for on/off-chip characterization of pulse-width limiter outputs 失效
标题翻译：用于脉宽限幅器输出的片外特性的系统和方法
公开(公告)号：US20060232310A1
公开(公告)日：2006-10-19
申请号：US11109090
申请日：2005-04-19
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/156 , G01R31/31708 , G01R31/31725 , H03K5/05 , H03K5/26
摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.
摘要翻译：本发明提供了用于表征脉冲宽度限制器输出的方法。接收已知的时钟信号。所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。第一中间信号被延迟已知的量以产生第一延迟信号。第一中间信号被反相以产生第一反相信号。通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。第二中间信号被延迟已知的量以产生第二延迟信号。对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。

52. 发明授权

US06958636B2 Charge leakage correction circuit for applications in PLLs 有权
标题翻译：针对PLL应用的充电泄漏校正电路
公开(公告)号：US06958636B2
公开(公告)日：2005-10-25
申请号：US10759942
申请日：2004-01-16
申请人： David William Boerstler , Franklin Manuel Baez , Eskinder Hailu
发明人： David William Boerstler , Franklin Manuel Baez , Eskinder Hailu
IPC分类号： H03K5/13 , H03L7/06 , H03L7/089
CPC分类号： H03L7/0891 , H03L7/0895
摘要： An apparatus, a method, and a computer program are provided for correcting charge in a Phased Lock Loop (PLL). Typically, PLL's utilize a Low Pass Filter (LPF). However, as a result of improvement of Complimentary Metal-Oxide on a Semiconductor (CMOS) technology charge leakage has become prevalent within LPFs. As a result, the method, apparatus, and computer program provide a device and/or methodology for correcting for charge leakage.
摘要翻译：提供了一种用于在相位锁定环（PLL）中校正电荷的装置，方法和计算机程序。通常，PLL使用低通滤波器（LPF）。然而，由于半导体（CMOS）技术上的免费金属氧化物的改进，电荷泄漏已经在LPF内普遍存在。因此，该方法，装置和计算机程序提供用于校正电荷泄漏的装置和/或方法。

53. 发明授权

US07969250B2 Structure for a programmable interpolative voltage controlled oscillator with adjustable range 失效
标题翻译：具有可调范围的可编程内插压控振荡器的结构
公开(公告)号：US07969250B2
公开(公告)日：2011-06-28
申请号：US12129811
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03B27/00
CPC分类号： H03L7/183 , H03L7/0998
摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.
摘要翻译：提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

54. 发明授权

US07917318B2 Structure for a duty cycle measurement circuit 有权
标题翻译：占空比测量电路的结构
公开(公告)号：US07917318B2
公开(公告)日：2011-03-29
申请号：US12129980
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G01R13/00
CPC分类号： H03K5/1565 , G01R31/31727
摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.
摘要翻译：提供了用于测量集成电路装置上任何地方的信号的绝对占空比的电路的设计结构。该电路具有多个基本上相同的脉冲整形器元件，每个脉冲整形器元件使占空比要被测量相同量的输入信号的脉冲扩展。脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为数据到触发器。触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。

55. 发明授权

US07895005B2 Duty cycle measurement for various signals throughout an integrated circuit device 有权
标题翻译：整个集成电路设备中各种信号的占空比测量
公开(公告)号：US07895005B2
公开(公告)日：2011-02-22
申请号：US11942966
申请日：2007-11-20
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G01R13/00
CPC分类号： G01R29/02 , G01R31/31725
摘要： A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.
摘要翻译：提供了用于测量集成电路设备上任何地方的信号的绝对占空比的机制。该机构采用具有多个基本相同的脉冲整形器元件的电路，每个脉冲整形器元件的占空比将被测量相同量的输入信号的脉冲。脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为数据到触发器。触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。

56. 发明申请

US20090183136A1 Structure for a Programmable Interpolative Voltage Controlled Oscillator with Adjustable Range 失效
标题翻译：具有可调范围的可编程插值电压控制振荡器的结构
公开(公告)号：US20090183136A1
公开(公告)日：2009-07-16
申请号：US12129811
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： G06F17/50
CPC分类号： H03L7/183 , H03L7/0998
摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.
摘要翻译：提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

57. 发明申请

US20090125262A1 Absolute Duty Cycle Measurement Method and Apparatus 有权
标题翻译：绝对占空比测量方法和装置
公开(公告)号：US20090125262A1
公开(公告)日：2009-05-14
申请号：US11938456
申请日：2007-11-12
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G01R29/00
CPC分类号： G01R31/31727 , G01R29/0273 , H03K5/1565
摘要： A method and apparatus for measuring the absolute duty cycle of a signal are provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.
摘要翻译：提供了用于测量信号的绝对占空比的方法和装置。选择来自信号源的非反相路径，并循环各种DCC电路设置索引，直到耦合到DCC电路的输出的分频器失效。然后，基于故障时的DCC电路的指标值来确定分路器故障时的第一最小脉冲宽度。选择来自信号源的反向路径，并且各种DCC电路设置索引再次循环，直到分频器失效。然后，基于该第二次故障时的DCC电路的指标值来确定分路器故障时的第二最小脉冲宽度。然后基于第一和第二最小脉冲宽度值的差来计算占空比。

58. 发明申请

US20080191809A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
公开(公告)号：US20080191809A1
公开(公告)日：2008-08-14
申请号：US12098483
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

59. 发明授权

US07358785B2 Apparatus and method for extracting a maximum pulse width of a pulse width limiter 失效
标题翻译：一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法
公开(公告)号：US07358785B2
公开(公告)日：2008-04-15
申请号：US11278842
申请日：2006-04-06
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。第11 / 109,090号（以下简称“090”）。在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

60. 发明申请

US20080012617A1 Duty Cycle Correction Circuit Whose Operation is Largely Independent of Operating Voltage and Process 有权
公开(公告)号：US20080012617A1
公开(公告)日：2008-01-17
申请号：US11457637
申请日：2006-07-14
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

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