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51. 发明申请

US20090108952A1 DISTORTION COMPENSATING CIRCUIT 有权
标题翻译：失真补偿电路
公开(公告)号：US20090108952A1
公开(公告)日：2009-04-30
申请号：US12342551
申请日：2008-12-23
申请人： Yoshito Shimizu , Noriaki Saito
发明人： Yoshito Shimizu , Noriaki Saito
IPC分类号： H03C1/00
CPC分类号： H04L27/367 , H03F1/3282
摘要： A distortion compensating circuit is provided in which, in the polar modulation system, while suppressing increase of compensation data and increase of the circuit scale, a modulated signal can be correctly expressed, or low-distortion characteristics of a power amplifier can be realized. Based on a steady characteristic compensating circuit 11 which stores an output signal amplitude and output phase characteristics with respect to a control voltage in a steady state, amplitude adjustment is executed on amplitude information r11(t) on which amplitude correction is performed, by a first amplitude information adjusting portion 13, whereby the output-response characteristics of an output signal amplitude of an amplifier with respect to a change of the control voltage can be improved.
摘要翻译：提供了一种失真补偿电路，其中在极坐标调制系统中，在抑制补偿数据的增加和电路规模的增加的同时，可以正确地表达调制信号，或者能够实现功率放大器的低失真特性。基于稳定特性补偿电路11，其以相对于稳定状态的控制电压存储输出信号振幅和输出相位特性，对其进行幅度校正的振幅信息r11（t）执行幅度调整，第一幅度信息调整部分13，从而可以提高放大器的输出信号幅度相对于控制电压变化的输出响应特性。

52. 发明申请

US20090023402A1 POLAR MODULATION CIRCUIT, INTEGRATED CIRCUIT AND RADIO APPARATUS 有权
标题翻译：极性调制电路，集成电路和无线电设备
公开(公告)号：US20090023402A1
公开(公告)日：2009-01-22
申请号：US11912169
申请日：2006-04-17
申请人： Yoshito Shimizu , Noriaki Saito
发明人： Yoshito Shimizu , Noriaki Saito
IPC分类号： H04B1/04 , H04B1/62
CPC分类号： H03F1/0222 , H03F1/3282
摘要： An object of the invention is to provide a polar modulation circuit capable of reducing the capacity of data stored in memory and suppressing an increase in the circuit scale related to distortion compensation while assuring the compensation accuracy. The polar modulation circuit according to the invention stores output signal characteristic relative to the control voltage at the steady state after input of the control voltage for a predetermined input amplitude of an input high frequency signal as the basis of distortion compensation of an amplifier separately into an offset storage section 101a which stores data used to add a predetermined DC offset voltage and a coefficient storage section 102 which stores data used for multiplication by a predetermined constant, thus reducing the circuit scale related to distortion compensation while assuring the compensation accuracy.
摘要翻译：本发明的目的是提供一种极性调制电路，其能够降低存储在存储器中的数据的容量，并且在确保补偿精度的同时抑制与失真补偿相关的电路规模的增加。根据本发明的极坐标调制电路将输入的高频信号的预定输入幅度的控制电压输入后的稳定状态下的输出信号特性存储为放大器的失真补偿的基础，偏移存储部分101a，其存储用于添加预定DC偏移电压的数据;以及系数存储部分102，其存储用于乘以预定常数的数据，从而在确保补偿精度的同时减小与失真补偿相关的电路规模。

53. 发明申请

US20070082629A1 Reception apparatus and reception method 有权
标题翻译：接收方式和接收方式
公开(公告)号：US20070082629A1
公开(公告)日：2007-04-12
申请号：US10581036
申请日：2004-11-30
申请人： Yoshito Shimizu , Noriaki Saito
发明人： Yoshito Shimizu , Noriaki Saito
IPC分类号： H01Q11/12
CPC分类号： H04W52/08 , H03G3/3052 , H04W52/10 , H04W52/143
摘要： A reception apparatus capable of preventing saturation and sensitivity degradation of a receiver when base transceiver station transmit power control is performed and calibrating offset voltage without increasing the amount of current consumption. In this apparatus, a gain setting section (109) estimates reception field intensity of each time slot in the next frame based on information of the reception field intensity and transmit power information which is information of the transmit power of the base transceiver station and calculates a gain set value according to the estimated reception field intensity. A gain control circuit (110) extracts a maximum gain out of the gains set by the gain setting section (109), uses the maximum gain as a set gain for DC offset voltage calibration and performs gain control at the gain set value corresponding to each time slot. A voltage calibration circuit (111) performs the DC offset voltage calibration of the received signal.
摘要翻译：当基站发射功率控制被执行并且校准失调电压而不增加电流消耗量时，能够防止接收机饱和和灵敏度退化的接收装置。在该装置中，增益设定部（109）基于作为基站的发射功率的信息的接收场强的信息和发送功率信息来估计下一帧中的每个时隙的接收场强，并且计算根据估计的接收场强度增益设定值。增益控制电路（110）从增益设定部（109）提取的增益中提取出最大增益，使用最大增益作为直流偏移电压校准的设定增益，并以对应于每个的增益设定值进行增益控制时隙。电压校准电路（111）对接收到的信号进行DC偏移电压校准。

54. 发明授权

US06331804B1 Amplifier and radio communication apparatus using the same 有权
标题翻译：放大器和使用它的无线电通信装置
公开(公告)号：US06331804B1
公开(公告)日：2001-12-18
申请号：US09487849
申请日：2000-01-19
申请人： Yoshito Shimizu , Noriaki Saito , Hiroyuki Yabuki
发明人： Yoshito Shimizu , Noriaki Saito , Hiroyuki Yabuki
IPC分类号： H03G330
CPC分类号： H03F3/191 , H03F2200/372 , H03G1/0088
摘要： In a cascade amplifier, the collector of a first transistor with a grounded emitter and the emitter of a second transistor are connected. A third transistor has the base grounded at radio frequency, the emitter connected to the base of the first transistor, and the collector connected to the collector of the second transistor. A fourth transistor connected to the emitter of the third transistor works as a constant current source. A bias changeover circuit supplies base biases of these transisiors. In this constitution, by using the bias changeover circuit for changing over the bias depending on the cut-off condition of the first transistor, the gain is changed over by making either the cascade amplifier or the third transistor operate.
摘要翻译：在级联放大器中，连接具有接地发射极和第二晶体管的发射极的第一晶体管的集电极。第三晶体管具有以射频接地的基极，发射极连接到第一晶体管的基极，并且集电极连接到第二晶体管的集电极。连接到第三晶体管的发射极的第四晶体管用作恒流源。偏置转换电路提供这些变压器的基极偏置。在这种结构中，通过使用偏置切换电路根据第一晶体管的截止条件来改变偏置，通过使级联放大器或第三晶体管工作来改变增益。

55. 发明授权

US08417203B2 Receiver and gain control method 有权
标题翻译：接收机和增益控制方法
公开(公告)号：US08417203B2
公开(公告)日：2013-04-09
申请号：US12810211
申请日：2008-12-16
申请人： Noriaki Saito
发明人： Noriaki Saito
IPC分类号： H04B1/06
CPC分类号： H03G3/3052
摘要： A receiver capable of performing optimum automatic gain control responsive to a peak factor of an input signal before subjected to A/D conversion is provided in a simple configuration. A peak detector 104 is placed at the later stage of a variable gain amplifier 102, two power determiners 107 and 108 different in threshold value are used, and the amplitude density is determined in three areas separated by two threshold values PDETL and PDETH, whereby it is made possible to identify the input signal having a peak factor different in modulation system and perform optimum gain control without A/D conversion of the input signal.
摘要翻译：以简单的结构提供能够响应于进行A / D转换之前的输入信号的峰值因子来执行最佳自动增益控制的接收机。峰值检测器104被放置在可变增益放大器102的后级，使用两个阈值不同的功率确定器107和108，并且在由两个阈值PDETL和PDETH隔开的三个区域中确定振幅密度，由此使得能够识别具有在调制系统中不同的峰值因数的输入信号，并且在没有输入信号的A / D转换的情况下执行最佳增益控制。

56. 发明申请

US20110199122A1 DIRECT SAMPLING CIRCUIT AND RECEIVER 有权
标题翻译：直接采样电路和接收器
公开(公告)号：US20110199122A1
公开(公告)日：2011-08-18
申请号：US13122475
申请日：2010-08-30
申请人： Yohei Morishita , Noriaki Saito
发明人： Yohei Morishita , Noriaki Saito
IPC分类号： H03H19/00 , H03K3/00
CPC分类号： H03H15/023 , H04B1/0007
摘要： A sampling circuit and a receiver with relatively simple configuration and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits (102-1 to 102-4), charging switch (1021) is controlled on and off using one of four-phase control signals. Rotate capacitor (1022) shares electrical charge accumulated in IQ generating circuit (101) via charging switch (1021). Dump switch (1023) is controlled on and off using a different signal from the control signal used to control charging switch (1021) on and off, among the four-phase control signals. Buffer capacitor (1026) shares electrical charge with rotate capacitor (1022) via dump switch (1023) to form an output value.
摘要翻译：提供具有相对简单的配置和时钟的采样电路和接收机，具有出色的频率特性。在离散时间电路（102-1至102-4）中，使用四相控制信号之一来控制充电开关（1021）的导通和截止。旋转电容器（1022）经由充电开关（1021）共享积分在IQ发生电路（101）中的电荷。在四相控制信号中，使用与用于控制充电开关（1021）的控制信号不同的信号来开启和关闭转储开关（1023）。缓冲电容器（1026）通过转储开关（1023）与旋转电容器（1022）共享电荷以形成输出值。

57. 发明申请

US20100260077A1 RADIO CIRCUIT DEVICE 审中-公开
标题翻译：无线电电路设备
公开(公告)号：US20100260077A1
公开(公告)日：2010-10-14
申请号：US12747349
申请日：2008-12-09
申请人： Toshifumi Nakatani , Satoshi Tsukamoto , Noriaki Saito
发明人： Toshifumi Nakatani , Satoshi Tsukamoto , Noriaki Saito
IPC分类号： H04B1/44
CPC分类号： H04B1/525
摘要： A radio circuit device capable of reducing a cross-modulation interference which occurs at a reception circuit due to a transmission signal leakage is provided.A transmission baseband circuit (12) for outputting a transmission signal, a reception circuit (14, 15) for receiving a reception signal as differential RF signals, an envelope signal generation circuit (24) for generating, from the transmission signal (12) outputted by the transmission baseband circuit, an envelope signal derived from a square of an envelope signal of the RF transmission signal, an envelope signal control circuit (20) for outputting a control signal to control an amplitude and a delay time of the envelope signal, and an envelope signal injection circuit (23) for controlling the amplitude and the delay time of the envelope signal in accordance with the control signal outputted from the envelope signal control circuit (20) and for injecting in phase the controlled envelope signal into each of the differential RF signals in the reception circuit (14, 15), are provided.
摘要翻译：提供一种能够降低由于传输信号泄漏而在接收电路处发生的交叉调制干扰的无线电电路装置。用于输出发送信号的发送基带电路（12），用于接收作为差分RF信号的接收信号的接收电路（14,15），从输出的发送信号（12）生成的包络信号生成电路（24）通过发送基带电路从RF发送信号的包络信号的平方得到的包络信号，用于输出控制信号以控制包络信号的振幅和延迟时间的包络信号控制电路（20），以及包络信号注入电路（23），用于根据从包络信号控制电路（20）输出的控制信号控制包络信号的幅度和延迟时间，并将受控包络信号同相分别注入每个差分提供接收电路（14,15）中的RF信号。

58. 发明申请

US20100224997A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100224997A1
公开(公告)日：2010-09-09
申请号：US12715826
申请日：2010-03-02
申请人： Noriaki Saito , Toyoji Sawada
发明人： Noriaki Saito , Toyoji Sawada
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/53223 , H01L22/32 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0392 , H01L2224/05083 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/0603 , H01L2224/45144 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.
摘要翻译：半导体器件包括设置在半导体衬底上的第一金属层; 设置在所述第一金属层上的绝缘层; 以及设置在绝缘层上并具有暴露于外部的电极焊盘表面的第二金属层，其中在所述绝缘层和所述第二金属层中设置有凹部; 并且至少第二金属层设置在绝缘层的凹部中。

59. 发明授权

US07580980B2 Email system restoring recipient identifier based on identifier-for-disclosure for establishing communication between sender and recipient 失效
标题翻译：电子邮件系统基于用于建立发送者和接收者之间的通信的标识符来恢复收件人标识符
公开(公告)号：US07580980B2
公开(公告)日：2009-08-25
申请号：US10538855
申请日：2003-12-19
申请人： Masahisa Kawashima , Fumitaka Hoshino , Akiko Fujimura , Shingo Kinoshita , Masayoshi Nakao , Noriaki Saito , Yukio Tsuruoka , Katsumi Takahashi , Tsuyoshi Abe , Jun Miyake
发明人： Masahisa Kawashima , Fumitaka Hoshino , Akiko Fujimura , Shingo Kinoshita , Masayoshi Nakao , Noriaki Saito , Yukio Tsuruoka , Katsumi Takahashi , Tsuyoshi Abe , Jun Miyake
IPC分类号： G06F15/16
CPC分类号： H04L51/28 , G06Q10/107 , H04L29/1215 , H04L29/12594 , H04L51/12 , H04L61/1564 , H04L61/301 , H04L61/307 , H04L63/0428 , H04M3/00
摘要： A recipient identifier and communication condition information stored in a recipient-identifier storing unit are encrypted by an identifier-for-disclosure creating unit of a recipient terminal to create an identifier-for-disclosure. An identifier-for-disclosure notifying unit notifies a sender terminal of the identifier-for-disclosure. When a communication request using the identifier-for-disclosure is sent from the recipient terminal, a restoring unit of a relay system extracts the communication condition information from the identifier-for-disclosure. Only when communication conditions included in the communication condition information are satisfied, communication between the recipient terminal and the sender terminal is established.
摘要翻译：存储在接收方 - 标识符存储单元中的收件人标识符和通信条件信息由接收方终端的用于公开的标识符创建单元加密以创建用于公开的标识符。通知标识符通知单元向发送者终端通知要被公开的标识符。当从接收终端发送使用用于公开的标识符的通信请求时，中继系统的恢复单元从公开标识符中提取通信条件信息。仅当满足通信条件信息中包括的通信条件时，才建立接收终端与发送方终端之间的通信。

60. 发明申请

US20050180076A1 Electrostatic discharge protection circuit 审中-公开
标题翻译：静电放电保护电路
公开(公告)号：US20050180076A1
公开(公告)日：2005-08-18
申请号：US10912150
申请日：2004-08-06
申请人： Noriaki Saito , Kenji Hashimoto
发明人： Noriaki Saito , Kenji Hashimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L27/02 , H01L29/78 , H02H3/20 , H02H9/00
CPC分类号： H01L27/0266
摘要： A space-saving electrostatic discharge protection circuit that protects an internal circuit effectively against an ESD. When a positive ESD voltage is applied to a power supply terminal VDD, a PMOS is in the on state for time determined by a time constant given by a first resistor and a capacitor and the voltage of a gate of an NMOS rises due to voltage generated across a second resistor. As a result, the potential of a substrate is raised, a parasitic bipolar transistor on the NMOS turns on at a low drain voltage, an electric current generated by the ESD flows to a power supply terminal VSS via a power supply line, and the internal circuit is protected.
摘要翻译：一种节省空间的静电放电保护电路，可有效防止内部电路抵抗ESD。当向电源端子VDD施加正的ESD电压时，PMOS由处于由第一电阻器和电容器给出的时间常数决定的时间处于导通状态，并且NMOS的栅极电压由于产生的电压而上升穿过第二个电阻。结果，衬底的电位升高，NMOS上的寄生双极晶体管在低漏极电压下导通，由ESD产生的电流通过电源线流到电源端子VSS，内部电路受到保护。

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