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51. 发明授权

US06921710B2 Technique for high efficiency metalorganic chemical vapor deposition 失效
公开(公告)号：US06921710B2
公开(公告)日：2005-07-26
申请号：US10757638
申请日：2004-01-13
申请人： Weimin Li , Sam Yang
发明人： Weimin Li , Sam Yang
IPC分类号： B05C11/00 , C23C16/18 , H01L21/02 , H10L21/20
CPC分类号： C23C16/45523 , C23C16/18 , H01L28/65
摘要： A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.

52. 发明申请

US20050009291A1 Methods for filling high aspect ratio trenches in semiconductor layers 失效
标题翻译：填充半导体层高纵横比沟槽的方法
公开(公告)号：US20050009291A1
公开(公告)日：2005-01-13
申请号：US10618220
申请日：2003-07-11
申请人： Jingyi Bai , Weimin Li , William Budge
发明人： Jingyi Bai , Weimin Li , William Budge
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76229
摘要： Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：提供了在半导体层中填充高纵横比沟槽的方法。该方法利用HDP-CVD工艺用沟槽填充材料填充沟槽。在这些方法中，气流和RF偏压被选择以提供对蚀刻比的高蚀刻，同时沟槽被部分填充。然后选择气体流量和RF偏压，以在沟槽完全填充时提供低的沉积比。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交的理解是不会用于解释或限制权利要求的范围或含义。

53. 发明授权

US06828683B2 Semiconductor devices, and semiconductor processing methods 有权
标题翻译：半导体器件和半导体处理方法
公开(公告)号：US06828683B2
公开(公告)日：2004-12-07
申请号：US09219041
申请日：1998-12-23
申请人： Weimin Li , Zhiping Yin
发明人： Weimin Li , Zhiping Yin
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/3185 , H01L21/76801 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between the conductive material and the second material. The barrier layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material. In another aspect, the invention encompasses a composition of matter comprising silicon chemically bonded to both nitrogen and an organic material. The nitrogen is not bonded to carbon. In yet another aspect, the invention encompasses a semiconductor processing method. A semiconductive substrate is provided and a layer is formed over the semiconductive substrate. The layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material.
摘要翻译：一方面，本发明包括一种半导体处理方法，其中在半导体衬底上形成导电含铜材料，并且在导电材料附近形成第二材料。在导电材料和第二材料之间形成阻挡层。阻挡层包括具有与氮和有机材料化学键合的硅的化合物。在另一方面，本发明包括包含与氮和有机材料化学键合的硅的物质组合物。氮不与碳结合。另一方面，本发明包括半导体处理方法。提供半导体衬底并且在半导体衬底上形成层。该层包括具有与氮和有机材料化学键合的硅的化合物。

54. 发明授权

US06815819B2 In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications 失效
标题翻译：用于半导体集成电路应用的化学气相沉积技术中的原位等离子体预沉积晶片处理
公开(公告)号：US06815819B2
公开(公告)日：2004-11-09
申请号：US10225974
申请日：2002-08-22
申请人： Weimin Li
发明人： Weimin Li
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/28568 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76868 , H01L21/76876 , Y10S438/974
摘要： A method of deoxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing to remove oxygen molecules from the surface to which adherence of the refractory metal. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

55. 发明授权

US06613656B2 Sequential pulse deposition 有权
公开(公告)号：US06613656B2
公开(公告)日：2003-09-02
申请号：US09782207
申请日：2001-02-13
申请人： Weimin Li
发明人： Weimin Li
IPC分类号： H01L2120
CPC分类号： C23C16/45527 , C23C16/4408 , C23C16/45523 , C23C16/52 , H01L21/28506
摘要： A method for growing films on substrates using sequentially pulsed precursors and reactants, system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method.

56. 发明授权

US06383951B1 Low dielectric constant material for integrated circuit fabrication 失效
标题翻译：用于集成电路制造的低介电常数材料
公开(公告)号：US06383951B1
公开(公告)日：2002-05-07
申请号：US09146397
申请日：1998-09-03
申请人： Weimin Li
发明人： Weimin Li
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C23C16/30 , C23C16/56 , H01L21/02211 , H01L21/02271 , H01L21/0234 , H01L21/02362 , H01L21/31612 , H01L21/76801
摘要： A method is provided for forming a material with a low dielectric constant, suitable for electrical isolation in integrated circuits. The material and method of manufacture has particular use as an interlevel dielectric between metal lines in integrated circuits. In a disclosed embodiment, methylsilane is reacted with hydrogen peroxide to deposit a silicon hydroxide layer incorporating carbon. The layer is then treated by exposure to a plasma containing oxygen, and annealing the layer at a temperature of higher than about 450° C. or higher.
摘要翻译：提供了一种形成具有低介电常数的材料的方法，适用于集成电路中的电隔离。该材料和制造方法特别用作集成电路中的金属线之间的层间电介质。在公开的实施方案中，甲基硅烷与过氧化氢反应以沉积包含碳的氢氧化硅层。然后通过暴露于含有氧的等离子体处理该层，并在高于约450℃或更高的温度下退火该层。

57. 发明授权

US06372643B1 Method for forming a selective contact and local interconnect in situ and semiconductor devices carrying the same 失效
标题翻译：用于形成选择性接触和局部互连原位以及携带其的半导体器件的方法
公开(公告)号：US06372643B1
公开(公告)日：2002-04-16
申请号：US09056309
申请日：1998-04-07
申请人： Christopher W. Hill , Weimin Li , Gurtej S. Sandhu
发明人： Christopher W. Hill , Weimin Li , Gurtej S. Sandhu
IPC分类号： H01L2144
CPC分类号： H01L21/28568 , C23C16/0272 , C23C16/44 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76877
摘要： A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of a semiconductor device structure may be treated in a plasma to enhance the adhesiveness of a selective contact thereto. The semiconductor device structure is positioned within a reaction chamber, wherein a selective contact is deposited onto the exposed semiconductor substrate regions, Any residual selective contact material may be removed from oxide surfaces either intermediately or after selective contact deposition. While the semiconductor device remains in the reaction chamber, a local interconnect is deposited over the semiconductor device structure. The local interconnect may then be patterned. Subsequent layers may be deposited over the local interconnect. The present invention also includes semiconductor device structures formed by the inventive process.
摘要翻译：用于在半导体衬底上原位形成选择性接触和局部互连的方法。可以在等离子体中处理半导体器件结构的暴露的半导体衬底区域以增强与其的选择性接触的粘合性。半导体器件结构位于反应室内，其中选择性接触沉积在暴露的半导体衬底区域上。任何残留的选择性接触材料可以在中间或选择性接触沉积之后从氧化物表面去除。当半导体器件保留在反应室中时，在半导体器件结构上沉积局部互连。然后可以对局部互连进行图案化。随后的层可以沉积在局部互连上。本发明还包括通过本发明方法形成的半导体器件结构。

58. 发明授权

US06326668B1 Semiconductor structure including metal nitride and metal silicide 失效
标题翻译：半导体结构包括金属氮化物和金属硅化物
公开(公告)号：US06326668B1
公开(公告)日：2001-12-04
申请号：US09285573
申请日：1999-04-02
申请人： Weimin Li
发明人： Weimin Li
IPC分类号： H01L2976
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/28556 , H01L21/76841 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76859
摘要： The present invention relates to a semiconductor structure including metal nitride and metal silicide, where a metal silicide layer is formed upon an active area that is part of a junction in order to facilitate further miniaturization that is demanded and dictated by the need for smaller devices. A single PECVD process makes three distinct depositions. First, a metal silicide forms by the reaction: MHal+Si+H2→MSix+HHal, where M represents a metal and Hal represents a preferred halogen or the like. Second, a metal nitride forms upon areas not containing Si by the reaction: MHal+N2+H2→MN+HHal. Third, a metal nitride forms upon areas of evolving metal silicide due to a diffusion barrier effect that makes formation of the metal silicide self limiting. Ultimately, a metal nitride layer will be uniformly disposed in a substantially uniform composition covering all underlying structures upon a semiconductor substrate. The inventive method can be used to form a semiconductor structure having a semiconductive substrate with an electrically active region therein, where a structure projects from the semiconductive substrate adjacent to the electrically active region. A first metal silicide is upon the electrically active region and a second metal silicide is upon the structure. A metal nitride layer extends continuously from the first metal silicide to the second metal silicide. An electrically conductive metallization material is upon the metal nitride layer.
摘要翻译：本发明涉及包括金属氮化物和金属硅化物的半导体结构，其中在作为结的一部分的有源区上形成金属硅化物层，以便于由需要较小器件所要求和规定的进一步小型化。单个PECVD过程产生三个不同的沉积。首先，通过以下反应形成金属硅化物：MHal + Si + H 2→MS xix + HHal，其中M表示金属，Hal表示优选的卤素等。第二，通过反应在不含Si的区域形成金属氮化物：MHal + N2 + H2-> MN + HHal。第三，由于扩散阻挡效应使得金属硅化物的形成在金属硅化物的区域上形成金属氮化物，从而形成金属硅化物自限制。最终，金属氮化物层将被均匀地布置成覆盖半导体衬底上的所有下面的结构的基本均匀的组成。本发明的方法可用于形成具有其中具有电活性区域的半导体衬底的半导体结构，其中结构从邻近电活性区域的半导体衬底突出。第一金属硅化物在电活性区上，第二金属硅化物在该结构上。金属氮化物层从第一金属硅化物连续延伸到第二金属硅化物。导电金属化材料在金属氮化物层上。

59. 发明授权

US06323101B1 Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers 失效
标题翻译：半导体处理方法，形成二氧化硅的方法形成沟槽隔离区域的方法以及形成层间电介质层的方法
公开(公告)号：US06323101B1
公开(公告)日：2001-11-27
申请号：US09146843
申请日：1998-09-03
申请人： Weimin Li , Trung Tri Doan , David L. Chapek
发明人： Weimin Li , Trung Tri Doan , David L. Chapek
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02337 , H01L21/3105 , H01L21/31612 , H01L21/76224
摘要： In one aspect, the invention includes a semiconductor processing method of removing water from a material comprising silicon, oxygen and hydrogen, the method comprising maintaining the material at a temperature of at least about 100° C., more preferably at least 300° C., and at a pressure of greater than 1 atmosphere to drive water from the material. In another aspect, the invention includes a semiconductor processing method of forming SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute comprising: a) forming a layer comprising Si(OH)x; b) maintaining the Si(OH)x at a temperature of at least about 300° C. and at a pressure of greater than 1 atmosphere to drive water from the Si(OH)x; and c) converting the Si(OH)x to SiO2, the SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute under the conditions of a buffered oxide etch utilizing 20:1 H2O:HF, at about atmospheric pressure and at a temperature of about 30° C. In another aspect, the invention includes a method of forming a trench isolation region comprising: a) forming a trench within a substrate; b) forming a layer comprising Si(OH)x within the trench and over the substrate; c) driving water from the layer comprising Si(OH)x at a pressure of greater than 1 atmosphere; d) converting the Si(OH)x to SiO2; and e) removing at least a portion of the SiO2.
摘要翻译：一方面，本发明包括从包括硅，氧和氢的材料中去除水的半导体加工方法，该方法包括将材料保持在至少约100℃，更优选至少300℃的温度。，并且在大于1个大气压的压力下驱动来自材料的水。在另一方面，本发明包括形成具有小于约700埃/分钟的湿蚀刻去除速率的SiO 2的半导体加工方法，包括：a）形成包含Si（OH）x的层; b）将Si（OH）x维持在至少约300℃的温度和大于1个大气压的压力下驱动来自Si（OH）x的水; 和c）在约大气压下在使用20:1 H 2 O:H HF的缓冲氧化物蚀刻的条件下，将Si（OH）x转化为SiO 2，SiO 2具有小于约700埃/分钟的湿蚀刻去除速率，以及在另一方面，本发明包括形成沟槽隔离区域的方法，包括：a）在衬底内形成沟槽; b）在沟槽内和衬底上形成包含Si（OH）x的层; c）在大于1大气压的压力下从含Si（OH）x的层驱动水; d）将Si（OH）x转化为SiO 2; 和e）除去SiO 2的至少一部分。

60. 发明申请

US20200227727A1 High Power Lithium Ion Battery and the Method to Form 审中-公开
公开(公告)号：US20200227727A1
公开(公告)日：2020-07-16
申请号：US16517598
申请日：2018-01-19
申请人： Weimin Li
发明人： Weimin Li
IPC分类号： H01M4/139 , H01M10/0525 , H01M4/04 , H01M4/36
摘要： A vertical ferroelectric NAND memory system and method of making is disclosed. The vertical ferroelectric NAND memory system may comprise a stack of horizontal layers and a vertical structure. The stack of horizontal layers may be formed on a semiconductor substrate. The stack of horizontal layers may comprise a plurality gate electrode layers alternating with a plurality of insulating layers. The gate electrode layer may comprise conductive lines alternate with insulating lines. The insulating lines may be formed of insulating materials. The conductive lines are formed of a metal comprising W. The vertical structure may extend vertically through the stack of horizontal layers. The vertical structure may comprise a ferroelectric oxide layer, a vertical channel structure. The vertical channel structure may be formed of a semiconductor material.

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