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51. 发明申请

US20060085606A1 Method and Related Apparatus for Internal Data Accessing of Computer System 有权
标题翻译：计算机系统内部数据访问方法及相关装置
公开(公告)号：US20060085606A1
公开(公告)日：2006-04-20
申请号：US11162407
申请日：2005-09-09
申请人： Andrew Su , Jiin Lai , Chad Tsai
发明人： Andrew Su , Jiin Lai , Chad Tsai
IPC分类号： G06F12/00
CPC分类号： G06F13/404
摘要： Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to system memory. Also responses from system memory and CPU will be buffered in the chipset respectively utilizing buffer resources of different virtual channels. By applying accessing routing dispatch, data accessing efficiency efficient will be increased.
摘要翻译：用于计算机系统的内部数据访问的方法和相关装置。在计算机系统中，外设可以通过或不侦听中央处理单元（CPU）来发出对系统内存空间的访问请求。在使用支持多个虚拟信道的芯片组服务于单个虚拟信道的外设的同时，本发明根据其窥探/非窥探属性将访问请求分配给不同的处理队列，使得读/非窥探请求被直接路由到系统存储器。来自系统存储器和CPU的响应也将分别利用不同虚拟通道的缓冲资源在芯片组中进行缓冲。通过应用访问路由调度，将提高数据访问效率。

52. 发明授权

US06820219B1 Integrated testing method for concurrent testing of a number of computer components through software simulation 有权
标题翻译：集成测试方法，通过软件仿真同时测试多台计算机组件
公开(公告)号：US06820219B1
公开(公告)日：2004-11-16
申请号：US09621750
申请日：2000-07-21
申请人： Hsiang-Chou Huang , Jiin Lai , Nai-Shung Chang
发明人： Hsiang-Chou Huang , Jiin Lai , Nai-Shung Chang
IPC分类号： G06F1100
CPC分类号： G06F11/261 , G06F11/263
摘要： An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.
摘要翻译：提出了一种综合测试方法，通过软件仿真以多任务方式同时对多个计算机组件执行测试程序。在该方法中，首先执行初始化过程以指定模拟操作的总数，FIFO缓冲器大小，命令序列和操作的开始时间。这种集成测试方法的一个特征是测试程序以多任务方式并行执行所有被测组件，以响应命令序列中的每个命令进行操作。在被测试的两个或更多个组件竞争相同资源的情况下，仲裁器被激活以对这些竞争组件执行仲裁。

53. 发明授权

US06717885B2 Switching circuit capable of improving memory write timing and method thereof 有权
标题翻译：能够改善存储器写入时序的开关电路及其方法
公开(公告)号：US06717885B2
公开(公告)日：2004-04-06
申请号：US10247664
申请日：2002-09-18
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： G11C700
CPC分类号： G06F13/1647 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4087
摘要： In DRAM system where quad rate transmission is used, at least one latch is disposed within a switching circuit for increasing the data valid windows of a portion of transmitted data segments. For example, in a sequence of transmitted data segments, only the odd numbered segments are having their data valid windows increased. Thereby, the writing process of the system is improved. The system further provides at least one delay circuit for suitably matching signals for a desired result.
摘要翻译：在使用四速率传输的DRAM系统中，在切换电路内设置至少一个锁存器，用于增加发送数据段的一部分的数据有效窗口。例如，在发送的数据段的序列中，只有奇数段的数据有效窗口增加。从而改善了系统的写入过程。该系统还提供至少一个延迟电路，用于为期望的结果适当地匹配信号。

54. 发明授权

US06308236B1 Local bus with dynamic decoding capability 失效
标题翻译：本地总线具有动态解码功能
公开(公告)号：US06308236B1
公开(公告)日：2001-10-23
申请号：US08498183
申请日：1995-07-05
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： G06F1314
CPC分类号： G06F13/404
摘要： The invention monitors the CPU cycle accessing the local bus device and records the address in its internal buffers. For any cycle addressed within a predetermined page of that address, the invention first stores the data into post-write buffer and thereafter immediately responds with READY signal to terminate the CPU cycle. For cycle addressed out of the predetermined page, this cycle would not have benefit from the post-write buffer and this new address value is recorded as a result and a new page is redefined dynamically if the address is responded by a local-bus device. The address page is dynamically defined at all time to meet the current behavior of the program running. Though a page miss could happen, however, the performance degradation is a minimal.
摘要翻译：本发明监视访问本地总线设备的CPU周期，并将地址记录在其内部缓冲器中。对于在该地址的预定页面内寻址的任何周期，本发明首先将数据存储到写入后缓冲器中，然后立即响应READY信号以终止CPU周期。对于从预定页面寻址的周期，该周期将不会受益于写入后缓冲器，并且如果地址由本地总线设备响应，则新的地址值被作为结果被记录并且动态地重新定义新的页面。地址页面始终是动态定义的，以满足程序运行的当前行为。然而，尽管可能会出现页面错误，但性能下降最小。

55. 发明授权

US08700859B2 Transfer request block cache system and method 有权
标题翻译：传输请求块缓存系统和方法
公开(公告)号：US08700859B2
公开(公告)日：2014-04-15
申请号：US12829343
申请日：2010-07-01
申请人： Shuang-Shuang Qin , Jiin Lai , Zhi-Qiang Hui , Xiu-Li Guo
发明人： Shuang-Shuang Qin , Jiin Lai , Zhi-Qiang Hui , Xiu-Li Guo
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB addresses in a system memory. A cache controller pre-fetches the TRBs and stores them in the cache according to the content of the mapping table.
摘要翻译：本发明涉及一种传输请求块（TRB）高速缓存系统和方法。高速缓存用于存储多个TRB，并且利用映射表将对应的TRB地址存储在系统存储器中。缓存控制器根据映射表的内容预取TRB并将其存储在缓存中。

56. 发明授权

US08504850B2 Method and controller for power management 有权
标题翻译：电源管理方法和控制器
公开(公告)号：US08504850B2
公开(公告)日：2013-08-06
申请号：US12358441
申请日：2009-01-23
申请人： Chung-Che Wu , Jiin Lai
发明人： Chung-Che Wu , Jiin Lai
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.
摘要翻译：一个系统的电源管理可以接收请求以进入系统的第一睡眠状态。响应于进入第一睡眠状态的请求，可以执行一个或多个进程以进入第一睡眠状态。响应于进入第一睡眠状态的请求以进入第二睡眠状态，系统的系统存储器可被存储在非易失性存储器（NVM）中。在将系统存储器存储在NVM中以响应于进入第一睡眠状态的请求时，可以将系统存储器中的电源移除。在取消系统内存的电源后，系统可能处于第二个睡眠状态。

57. 发明授权

US08386908B2 Data transmission methods and universal serial bus host controllers utilizing the same 有权
标题翻译：数据传输方法和通用串行总线主机控制器
公开(公告)号：US08386908B2
公开(公告)日：2013-02-26
申请号：US12872526
申请日：2010-08-31
申请人： Xingchen Chen , Jiin Lai , Di Dai , Shanna Pang
发明人： Xingchen Chen , Jiin Lai , Di Dai , Shanna Pang
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F13/28
摘要： A data transmission method for a universal serial bus (USB) host controller is provided. First, input data is received. A cyclic redundancy check (CRC) result of the input data is calculated, and, simultaneously, the input data is transmitted to a system memory of a host. Then, it is determined whether the input data is the last input data of a data packet. When it is determined that the input data is the last input data of the data packet, the CRC result of the last input data of the data packet is calculated. Thus, the CRC result of the data packet is accumulated. The accumulated CRC result is combined with the last input data, and transmitted the combination to the system memory of the host.
摘要翻译：提供了一种用于通用串行总线（USB）主机控制器的数据传输方法。首先，接收输入数据。计算输入数据的循环冗余校验（CRC）结果，同时将输入数据发送到主机的系统存储器。然后，确定输入数据是否是数据分组的最后输入数据。当确定输入数据是数据分组的最后输入数据时，计算数据分组的最后输入数据的CRC结果。因此，累积了数据分组的CRC结果。累积CRC结果与最后一个输入数据组合，并将组合传输到主机的系统存储器。

58. 发明申请

US20110099305A1 Universal Serial Bus Host Control Methods and Universal Serial Bus Host Controllers 有权
标题翻译：通用串行总线主机控制方法和通用串行总线主机控制器
公开(公告)号：US20110099305A1
公开(公告)日：2011-04-28
申请号：US12906431
申请日：2010-10-18
申请人： Di Dai , Jiin Lai , Zhiqiang Hui , Shanna Pang
发明人： Di Dai , Jiin Lai , Zhiqiang Hui , Shanna Pang
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.
摘要翻译： USB主机控制器提供USB主机控制方式。 USB主机控制器包括USB设备和缓冲器，USB设备包括一个或多个端点。 USB主机控制方法包括以下步骤：将要发送到第一端点的第一输出数据存储为用于第一端点的一个或多个缓冲单元; 将第一输出数据发送到第一端点; 并且当接收到来自所述第一端点的第一预定响应时，配置与所述一个或多个缓冲器单元中的所述第一端点对应的假释放标签和信息标签，并且不释放所述一个或多个缓冲器单元。

59. 发明申请

US20110093640A1 Universal Serial Bus Host Controller and Control Method Thereof 有权
标题翻译：通用串行总线主机控制器及其控制方法
公开(公告)号：US20110093640A1
公开(公告)日：2011-04-21
申请号：US12900309
申请日：2010-10-07
申请人： Zhiqiang Hui , Jiin Lai , Shanna Pang , Di Dai
发明人： Zhiqiang Hui , Jiin Lai , Shanna Pang , Di Dai
IPC分类号： G06F13/36
CPC分类号： G06F13/385 , G06F2213/3812
摘要： A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.
摘要翻译：提供USB主机控制器。 USB主机控制器能够与具有端点的多个USB设备通信，并向第一端点发送请求。 USB主机控制器包括第一存储器和第一控制单元。当第一端点响应于该请求发出未获得的事务分组时，第一控制单元将端点信息从第一端点存储到第一存储器中。未完成的事务数据包指示第一个端点尚未就绪。

60. 发明授权

US07779215B2 Method and related apparatus for accessing memory 有权
标题翻译：用于访问存储器的方法和相关装置
公开(公告)号：US07779215B2
公开(公告)日：2010-08-17
申请号：US10906748
申请日：2005-03-04
申请人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
发明人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G11C2207/2281
摘要： A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.
摘要翻译：提供了一种在不对称布置的存储器中利用多通道传输带宽的方法。本发明将存储器的存储器级别的对称布置部分定义为虚拟等级。如果数据存储在存储器的对称布置的存储器级中，则对应于对称排列的存储器级别的通道可以同时用于传送数据。如果数据被存储在存储器的不对称排列的存储器级中，则对应于不对称布置的存储器级的通道只能用于传送数据。

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