专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08634550B2 Architecture and instruction set for implementing advanced encryption standard (AES) 有权
标题翻译：实现高级加密标准（AES）的体系结构和指令集
公开(公告)号：US08634550B2
公开(公告)日：2014-01-21
申请号：US13088088
申请日：2011-04-15
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28 , G06F15/00 , G06F12/14
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

52. 发明申请

US20140019694A1 PARALLELL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单数据缓冲器的并行处理
公开(公告)号：US20140019694A1
公开(公告)日：2014-01-16
申请号：US13631763
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的填充数据段，将数据段流传输到数据寄存器中，并且并行地对每个段执行串行数据处理算法。

53. 发明申请

US20140006753A1 MATRIX MULTIPLY ACCUMULATE INSTRUCTION 有权
标题翻译：矩阵多项累积指令
公开(公告)号：US20140006753A1
公开(公告)日：2014-01-02
申请号：US13995453
申请日：2011-12-22
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , G06F9/3001 , G06F9/30036 , H04L9/0643
摘要： A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.
摘要翻译：描述了一种方法。该方法包括对存储在第三寄存器中的结果矩阵中的每个位置迭代执行，将存储在第一寄存器中的矩阵位置处的值乘以存储在第二寄存器中的矩阵位置处的值，以获得第一乘法值，其中第一寄存器和第二寄存器中的位置由结果矩阵中的位置确定，并且执行具有第一乘法值的异或（XOR）操作和存储在存储在第三寄存器中的结果矩阵位置处的值以获得结果值。

54. 发明授权

US08607129B2 Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic 有权
公开(公告)号：US08607129B2
公开(公告)日：2013-12-10
申请号：US13175500
申请日：2011-07-01
申请人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
发明人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： G06F11/10 , G06F11/1076 , H03M1/1052 , H03M7/42 , H03M13/09 , H03M13/091 , H03M13/158 , H03M13/6575
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

55. 发明申请

US20130290285A1 DIGEST GENERATION 有权
标题翻译：最终生成
公开(公告)号：US20130290285A1
公开(公告)日：2013-10-31
申请号：US13995236
申请日：2011-11-01
申请人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
发明人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30306 , G06F17/3033
摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
摘要翻译：在一个实施例中，电路可以生成待组合的摘要以产生散列值。摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

56. 发明申请

US20130275722A1 METHOD AND APPARATUS TO PROCESS KECCAK SECURE HASHING ALGORITHM 有权
标题翻译：过程KECCAK安全冲洗算法的方法和设备
公开(公告)号：US20130275722A1
公开(公告)日：2013-10-17
申请号：US13976184
申请日：2011-12-13
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , H04L9/0643 , H04L2209/122
摘要： A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.
摘要翻译：处理器包括多个寄存器，指令解码器，用于接收处理表示KECCAK散列算法的KECCAK状态的数据的KECCAK状态立方体的指令，以将KECCAK状态立方体分割成多个子多维数据集，并存储子管道分别在多个寄存器中，以及执行单元，其耦合到指令解码器，以向量方式分别存储在多个寄存器中的多个子区上执行KECCAK散列算法。

57. 发明授权

US08380777B2 Normal-basis to canonical-basis transformation for binary galois-fields GF(2m) 有权
标题翻译：二进制Galois-field的典型基变换法（2m）
公开(公告)号：US08380777B2
公开(公告)日：2013-02-19
申请号：US11772176
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：对于通用多项式和以所有形式的所有形式的特殊不可约多项式提供了从正常形式到规范形式的基础转换，称为全要素多项式（AOP）。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

58. 发明申请

US20130007573A1 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC 有权
标题翻译：有效和可扩展的循环冗余使用GALOIS-FIELD ARTIMETIC检查电路
公开(公告)号：US20130007573A1
公开(公告)日：2013-01-03
申请号：US13175500
申请日：2011-07-01
申请人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
发明人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/10 , G06F11/1076 , H03M1/1052 , H03M7/42 , H03M13/09 , H03M13/091 , H03M13/158 , H03M13/6575
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
摘要翻译：本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

59. 发明授权

US08073892B2 Cryptographic system, method and multiplier 有权
标题翻译：加密系统，方法和乘数
公开(公告)号：US08073892B2
公开(公告)日：2011-12-06
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F7/52
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数具有多个段的操作数。所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二操作数已被提供给第一个操作数的每个段。该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。乘法器还包括耦合到逻辑的累加器。

60. 发明授权

US07986779B2 Efficient elliptic-curve cryptography based on primality of the order of the ECC-group 有权
标题翻译：基于ECC组的顺序的有效椭圆曲线加密
公开(公告)号：US07986779B2
公开(公告)日：2011-07-26
申请号：US11772170
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , G06F7/72
CPC分类号： G06F7/725 , G06F5/01
摘要： Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.
摘要翻译：通过最小化移位操作的数量来减少执行用于ECC的标量点乘法的时间。通过基于ECC组的顺序的基本原理执行中间计算的点的选择性比较，通过应用模量缩放来最小化这些操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式