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51. 发明授权

US07391064B1 Memory device with a selection element and a control line in a substantially similar layer 有权
标题翻译：具有选择元件和控制线的存储器件在基本相似的层中
公开(公告)号：US07391064B1
公开(公告)日：2008-06-24
申请号：US11001519
申请日：2004-12-01
申请人： Nicholas H. Tripsas , Suzette Pangrle
发明人： Nicholas H. Tripsas , Suzette Pangrle
IPC分类号： H01L29/80
CPC分类号： H01L27/1021 , H01L27/101
摘要： The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.
摘要翻译：本发明有利于通过减少实现半导体存储器件所需的层数来制造半导体存储器组件。本发明提供了一种选择元件，其形成在与控制线之一（例如字线和位线之一）相同的层中。在本发明的一个实施例中，二极管被实现为与控制线之一在同一层内的选择元件。生产作为字线和位线之一的同一层内的选择元件可减少与垂直堆叠相关的问题，提高了设备产量并降低了相关生产成本。本发明还提供了一种生产存储器件的有效方法，其中选择元件与控制线之一在同一层中。

52. 发明授权

US06803272B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices 有权
标题翻译：在改性ONO结构中使用高K介电材料用于半导体器件
公开(公告)号：US06803272B1
公开(公告)日：2004-10-12
申请号：US10646080
申请日：2003-08-22
申请人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
发明人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
IPC分类号： H01L218242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/7923
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.
摘要翻译：一种制造包括修饰的ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一氧化物层; 在所述第一氧化物层上沉积包含高K电介质材料的层; 以及在包含高K电介质材料的层上形成顶部氧化物层。半导体器件可以是例如MIRRORBIT TM 2位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

53. 发明授权

US06500713B1 Method for repairing damage to charge trapping dielectric layer from bit line implantation 有权
标题翻译：修复来自位线植入的电荷捕获电介质层损伤的方法
公开(公告)号：US06500713B1
公开(公告)日：2002-12-31
申请号：US10023349
申请日：2001-12-20
申请人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal
发明人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/268 , H01L27/115
摘要： A method of forming a buried bit in line in MONOS cell implants dopant into a substrate through a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer. The implantation process damages the ONO layer. A laser thermal annealing process repairs the damage to the ONO layer, so that leakage between the buried bit line formed during the implantation process and a control gate formed after the laser thermal annealing is complete is avoided.
摘要翻译：在MONOS单元中通过诸如氧化物 - 氧化物 - 氧化物（ONO）层的电荷捕获介电层将掺杂剂埋入衬底中的方法。植入过程损害ONO层。激光热退火工艺修复对ONO层的损伤，从而避免了在注入过程中形成的掩埋位线与在激光热退火之后形成的控制栅极之间的泄漏完成。

54. 发明授权

US06410956B1 Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
标题翻译：使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统
公开(公告)号：US06410956B1
公开(公告)日：2002-06-25
申请号：US09478864
申请日：2000-01-07
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L2976
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。至少一个栅极堆叠具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入存放至少一个栅极堆叠具有边缘。所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个在间隔物沉积之后在半导体中的漏极注入。至少一个门具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

55. 发明授权

US06355933B1 Ion source and method for using same 有权
标题翻译：离子源及其使用方法
公开(公告)号：US06355933B1
公开(公告)日：2002-03-12
申请号：US09229326
申请日：1999-01-13
申请人： Nicholas H. Tripsas , Robert B. Ogle, Jr.
发明人： Nicholas H. Tripsas , Robert B. Ogle, Jr.
IPC分类号： H01J3708
CPC分类号： H01J27/08 , H01J37/08 , H01J2237/022 , H01J2237/31701
摘要： Damaging forming deposits and etching is reduced in an ion source by introducing an oxygenated gas during operation of the ion source. Embodiments include an ion source in fluid communication with a source of oxygenated gas and introducing about 1% to about 10% of carbondioxide as the oxygenated gas together with a feed material.
摘要翻译：通过在离子源的操作期间引入氧化气体，在离子源中减少形成沉积物和腐蚀。实施例包括与氧化气体源流体连通的离子源，并将约1％至约10％的二氧化碳作为含氧气体与进料一起引入。

56. 发明授权

US6034395A Semiconductor device having a reduced height floating gate 失效
标题翻译：具有减小的高度浮动栅极的半导体器件
公开(公告)号：US6034395A
公开(公告)日：2000-03-07
申请号：US92352
申请日：1998-06-05
申请人： Nicholas H. Tripsas , Effiong Ibok , Tuan Duc Pham
发明人： Nicholas H. Tripsas , Effiong Ibok , Tuan Duc Pham
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously reducing the height of the floating gates in particular locations. The reduced height floating gate's topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的布置。通过有利地减小浮动门在特定位置的高度，这种布置有效地降低了归结于相邻浮动栅之间的空间的拓扑的严重性。降低的浮动栅极的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的布置可防止控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

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