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51. 发明公开

US20240029775A1 SEMICONDUCTOR-ELEMENT-INCLUDING MEMORY DEVICE 审中-公开
公开(公告)号：US20240029775A1
公开(公告)日：2024-01-25
申请号：US18222116
申请日：2023-07-14
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： G11C11/403 , G11C11/4096 , G11C11/4097 , H10B12/00
CPC分类号： G11C11/403 , G11C11/4096 , G11C11/4097 , H10B12/20
摘要： A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.

52. 发明公开

US20230337410A1 PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20230337410A1
公开(公告)日：2023-10-19
申请号：US18330064
申请日：2023-06-06
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA
IPC分类号： H10B10/00 , H01L29/423
CPC分类号： H10B10/125 , H01L29/42392
摘要： A contact hole is formed on a boundary region between an N+ layer connected to a bottom part of a Si pillar forming a select transistor SGT and a P+ layer connected to a bottom part of a Si pillar forming a load transistor SGT on an X-X′ line and on a gate TiN layer surrounding a Si pillar forming a load transistor SGT on an XX-XX′ line in an SRAM cell. A conductor W layer is formed in a bottom part of the contact hole. A SiO2 layer including a hole is formed inside the contact hole on the W layer.

53. 发明公开

US20230320065A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20230320065A1
公开(公告)日：2023-10-05
申请号：US18190511
申请日：2023-03-27
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

54. 发明公开

US20230276612A1 MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20230276612A1
公开(公告)日：2023-08-31
申请号：US18311701
申请日：2023-05-03
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA
IPC分类号： H10B12/00
CPC分类号： H10B12/20 , H10B12/01
摘要： On P layer bases extending in a band shape in a first direction in plan view, N+ layers also extending in a band shape in the first direction and Si pillars are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, contact holes whose bottom portions are in contact with the N+ layers are formed in an insulating layer, and first conductor W layers are formed at the bottom portions of the contact holes. Subsequently, insulating layers each having a hole are formed in the contact holes. Subsequently, a second conductor W layer is formed in a second direction perpendicular to the first direction so as to be connected to the gate conductor layers.

55. 发明公开

US20230268413A1 PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20230268413A1
公开(公告)日：2023-08-24
申请号：US18309002
申请日：2023-04-28
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA
IPC分类号： H01L29/423 , H01L27/088 , H01L29/06 , H01L29/786 , H01L29/775 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/42392 , H01L27/088 , H01L29/0673 , H01L29/78696 , H01L29/775 , H01L29/66439 , H01L21/823412
摘要： On a semiconductor base that extends in a band shape in a direction (first direction) perpendicular to a line X-X′ direction (second direction) in plan view, an N+ layer, a P+ layer, and Si pillars that also extend in a band shape in the first direction are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, a contact hole whose bottom portion is in contact with the N+ layer and the P+ layer is formed in an insulating layer, and a first conductor W layer is formed at the bottom portion of the contact hole. Subsequently, an insulating layer that has a hole is formed in the contact hole. Subsequently, a second conductor W layer is formed in the line X-X′ direction so as to be connected to the gate conductor layers.

56. 发明申请

US20230011973A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 有权
公开(公告)号：US20230011973A1
公开(公告)日：2023-01-12
申请号：US17858574
申请日：2022-07-06
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108 , G11C5/06
摘要： A P layer 2 having a band shape is on an insulating substrate 1. An N+ layer 3a connected to a first source line SL1 and an N+ layer 3b connected to a first bit line are on respective sides of the P layer 2 in a first direction parallel to the insulating substrate. A first gate insulating layer 4a surrounds a portion of the P layer 2 connected to the N+ layer 3a, and a second gate insulating layer 4b surrounds the P layer 2 connected to the N+ layer 3b. A first gate conductor layer 5a connected to a first plate line and a second gate conductor layer 5b connected to a second plate line are isolated from each other and cover two respective side surfaces of the first gate insulating layer 4a in a second direction perpendicular to the first direction. A third gate conductor layer 5c connected to a first word line surrounds the second gate insulating layer 4b. These components constitute a dynamic flash memory.

57. 发明申请

US20220392900A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20220392900A1
公开(公告)日：2022-12-08
申请号：US17884820
申请日：2022-08-10
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108 , G11C11/404 , G11C11/4096
摘要： There are an N+ layer connected to a source line SL and an N+ layer connected to a bit line BL at both ends of a Si pillar standing on a substrate in a perpendicular direction, a P+ layer connected to the N+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connected to a plate line PL, and a second gate conductor layer surrounding a gate HfO2 layer surrounding the Si pillar and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current inside a channel region of the Si pillar and a data erase operation of removing the group of holes from the channel region.

58. 发明申请

US20220367679A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENTS 有权
公开(公告)号：US20220367679A1
公开(公告)日：2022-11-17
申请号：US17740656
申请日：2022-05-10
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/12 , H01L29/78 , H01L29/786
摘要： Provided on a substrate 1 are an N+ layer connecting to a source line SL, a first Si pillar as a P+ layer standing in an upright position along the vertical direction, and a second Si pillar as a P layer. An N+ layer connecting to a bit line BL is provided on the second Si pillar. A first gate insulating layer is provided so as to surround the first Si pillar, and a second gate insulating layer is provided so as to surround the second Si pillar. A first gate conductor layer connecting to a plate line PL is provided so as to surround the first insulating layer, and a second gate conductor layer connecting to a word line WL is provided so as to surround the second insulating layer. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data write operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region, and a data erase operation for removing the holes from the channel region.

59. 发明申请

US20220367473A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 有权
公开(公告)号：US20220367473A1
公开(公告)日：2022-11-17
申请号：US17872279
申请日：2022-07-25
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108 , G11C11/404 , G11C11/408 , G11C11/4091 , G11C11/4096
摘要： In a memory device, pages are arrayed in a column direction, each page constituted by memory cells arrayed in row direction on an insulating substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer 3b, respectively. One side surface and the other side surface of the gate insulating layer are covered with a gate conductor layer continuous with a first plate line and a gate conductor layer continuous with a second plate line, respectively. A gate conductor layer continuous with a word line surrounds the gate insulating layer.

60. 发明申请

US20220367471A1 SEMICONDUCTOR-ELEMENT-INCLUDING MEMORY DEVICE 有权
公开(公告)号：US20220367471A1
公开(公告)日：2022-11-17
申请号：US17743115
申请日：2022-05-12
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108 , G11C11/404 , G11C11/4091 , G11C11/4096
摘要： A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page sum-of-products read operation, a voltage is applied to the driving control line such that memory cell currents, in the group of memory cells, flowing into the bit lines multiply N-fold (N is a positive integer).

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