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51. 发明申请

US20080079094A1 Methods for inducing strain in non-planar transistor structures 有权
标题翻译：在非平面晶体管结构中诱导应变的方法
公开(公告)号：US20080079094A1
公开(公告)日：2008-04-03
申请号：US11540863
申请日：2006-09-29
申请人： Been-Yih Jin , Brian Doyle , Uday Shah , Jack Kavalieros
发明人： Been-Yih Jin , Brian Doyle , Uday Shah , Jack Kavalieros
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.
摘要翻译：用于在非平面晶体管的沟道区域中诱导压缩应变的方法以及通过这种方法形成的器件和系统。在一个实施例中，一种方法可以包括在与栅极结构间隔物相邻的半导体本体中形成沟槽。半导体本体可以位于衬底上并且在相对于衬底的不同平面中。栅极结构可以位于半导体本体和硅片上并且垂直于半导体本体。在衬底上形成半导体本体和栅极结构之后，电介质材料可以共形沉积在衬底上并被蚀刻以在半导体本体和栅极结构上形成间隔物。可以对衬底进行图案化和蚀刻，以在与栅极结构上的间隔物相邻的半导体本体中形成沟槽。可以将应变材料引入到沟槽中。

52. 发明授权

US08502351B2 Nonplanar device with thinned lower body portion and method of fabrication 有权
公开(公告)号：US08502351B2
公开(公告)日：2013-08-06
申请号：US13243441
申请日：2011-09-23
申请人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
发明人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
IPC分类号： H01L29/06
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

53. 发明申请

US20070257325A1 Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof 有权
标题翻译：具有保形PVD功能金属的三栅极器件及其制造方法
公开(公告)号：US20070257325A1
公开(公告)日：2007-11-08
申请号：US11418295
申请日：2006-05-03
申请人： Willy Rachmady , Brian Doyle , Jack Kavalieros , Uday Shah
发明人： Willy Rachmady , Brian Doyle , Jack Kavalieros , Uday Shah
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
摘要翻译：一种制造三栅极半导体器件的方法，包括具有上表面和侧表面的半导体本体和在上表面和侧表面上具有大致相同厚度的金属栅极。本文描述了具有保形物理气相沉积功能金属的三栅极器件在其三维体上的实施例。可以描述和要求保护其他实施例。

54. 发明授权

US08067818B2 Nonplanar device with thinned lower body portion and method of fabrication 有权
标题翻译：具有减薄的下体部分的非平面装置和制造方法
公开(公告)号：US08067818B2
公开(公告)日：2011-11-29
申请号：US12954241
申请日：2010-11-24
申请人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
发明人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
IPC分类号： H01L29/06
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

55. 发明申请

US20110062512A1 NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION 有权
标题翻译：具有较薄体部分的非平面装置和制造方法
公开(公告)号：US20110062512A1
公开(公告)日：2011-03-17
申请号：US12954241
申请日：2010-11-24
申请人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
发明人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
IPC分类号： H01L29/78
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

56. 发明申请

US20180350418A1 MEMORY CELLS WITH ENHANCED TUNNELING MAGNETORESISTANCE RATIO, MEMORY DEVICES AND SYSTEMS INCLUDING THE SAME 审中-公开
公开(公告)号：US20180350418A1
公开(公告)日：2018-12-06
申请号：US15779029
申请日：2015-12-24
申请人： Brian S. Doyle , Elijah V. Karpov , Kaan Oguz , Kevin P. O'Brien , Charles C. Kuo , Mark L. Doczy , Uday Shah , Yih Wang
发明人： Brian S. Doyle , Elijah V. Karpov , Kaan Oguz , Kevin P. O'Brien , Charles C. Kuo , Mark L. Doczy , Uday Shah , Yih Wang
IPC分类号： G11C11/16 , G11C11/56 , H01L43/08 , H01L27/22
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5615 , H01L27/228 , H01L43/08
摘要： Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.

57. 发明授权

US09548449B2 Conductive oxide random access memory (CORAM) cell and method of fabricating same 有权
标题翻译：导电氧化物随机存取存储器（CORAM）单元及其制造方法
公开(公告)号：US09548449B2
公开(公告)日：2017-01-17
申请号：US13925951
申请日：2013-06-25
申请人： Elijah V. Karpov , Brian S. Doyle , Uday Shah , Robert S. Chau
发明人： Elijah V. Karpov , Brian S. Doyle , Uday Shah , Robert S. Chau
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1266
摘要： Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory element includes a first conductive electrode. An insulating layer is disposed on the first conductive oxide and has an opening with sidewalls therein that exposes a portion of the first conductive electrode. A conductive oxide layer is disposed in the opening, on the first conductive electrode and along the sidewalls of the opening. A second electrode is disposed in the opening, on the conductive oxide layer.
摘要翻译：描述了导电氧化物随机存取存储器（CORAM）单元和制造CORAM单元的方法。例如，用于存储元件的材料层堆叠包括第一导电电极。绝缘层设置在第一导电氧化物上并且具有露出第一导电电极的一部分的侧壁的开口。导电氧化物层设置在开口中，在第一导电电极上并且沿着开口的侧壁。第二电极设置在开口中，在导电氧化物层上。

58. 发明授权

US09166150B2 Electric field enhanced spin transfer torque memory (STTM) device 有权
标题翻译：电场增强自旋转矩记忆（STTM）装置
公开(公告)号：US09166150B2
公开(公告)日：2015-10-20
申请号：US13725235
申请日：2012-12-21
申请人： Brian S. Doyle , Charles C. Kuo , David L. Kencke , Roksana Golizadeh Mojarad , Uday Shah
发明人： Brian S. Doyle , Charles C. Kuo , David L. Kencke , Roksana Golizadeh Mojarad , Uday Shah
IPC分类号： G11C11/00 , H01L43/12 , H01L43/08 , G11C11/155 , G11C11/16 , H01L27/22
CPC分类号： H01L43/02 , G11C11/155 , G11C11/161 , G11C11/1675 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
摘要翻译：具有用于施加电场的场板的旋转转矩存储器（STTM）装置，以减少传递转矩感应磁化切换所需的临界电流。实施例不仅利用电流感应磁场或自旋转移转矩，还利用电场诱导的磁偶极取向的操纵来设置磁性器件元件中的状态（例如，写入存储元件）。由MTJ电极和场板之间的电压差产生的电场向磁性隧道结（MTJ）的自由磁性层施加电场，以在至少一部分自由磁性层上调制一个或多个磁性能。

59. 发明授权

US08987091B2 III-N material structure for gate-recessed transistors 有权
标题翻译：用于栅极 - 凹槽晶体管的III-N材料结构
公开(公告)号：US08987091B2
公开(公告)日：2015-03-24
申请号：US13976840
申请日：2011-12-23
申请人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
发明人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L31/00 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02252 , H01L21/02255 , H01L21/02258 , H01L21/02458 , H01L21/0254 , H01L21/268 , H01L21/30604 , H01L21/30612 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/365 , H01L29/401 , H01L29/4236 , H01L29/512 , H01L29/518 , H01L29/66462
摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
摘要翻译：具有凹入栅极的III-N晶体管。外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和III-N沟道层之间的III-N蚀刻停止层。蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化物的凹陷栅III-N MOS-HEMT。可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

60. 发明申请

US20140239358A1 NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION 审中-公开
标题翻译：具有较薄体部分的非平面装置和制造方法
公开(公告)号：US20140239358A1
公开(公告)日：2014-08-28
申请号：US14273373
申请日：2014-05-08
申请人： Uday Shah , Brian S. Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
发明人： Uday Shah , Brian S. Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
IPC分类号： H01L29/78
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

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