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51. 发明授权

US07888216B2 Method of fabricating a high performance power MOS 有权
标题翻译：制造高性能功率MOS的方法
公开(公告)号：US07888216B2
公开(公告)日：2011-02-15
申请号：US12757242
申请日：2010-04-09
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.
摘要翻译：制造半导体器件的方法包括在衬底中形成包括第一类掺杂剂的阱区; 在所述阱区中形成包含不同于所述第一类型掺杂剂的第二类型掺杂剂的基极区; 以及在包括第一类型掺杂剂的衬底源极和漏极区域中形成。该方法还包括在衬底上形成横向插入在源区和漏区之间的栅电极; 以及在所述衬底上形成栅极间隔件，所述栅极间隔件横向设置在所述源区域和所述栅电极之间，邻近所述栅电极的一侧并且具有嵌入其中的导电特征。阱区域围绕漏极区域和基极区域，并且基极区域部分地设置在围绕源极区域的栅极电极周围，该源极区域限定栅极电极下方的沟道，其长度基本上小于栅电极的长度的一半。

52. 发明申请

US20100006935A1 Breakdown Voltages of Ultra-High Voltage Devices By Forming Tunnels 有权
标题翻译：通过形成隧道的超高压器件的故障电压
公开(公告)号：US20100006935A1
公开(公告)日：2010-01-14
申请号：US12170246
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

53. 发明申请

US20090085101A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20090085101A1
公开(公告)日：2009-04-02
申请号：US12329285
申请日：2008-12-05
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0878 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.
摘要翻译：提供具有高击穿电压和低导通电阻的半导体器件。一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。晶体管的源极和漏极区位于高压P阱和高压N阱中。可选地，在场电介质下的N阱区域中形成P场环。在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

54. 发明授权

US07476591B2 Lateral power MOSFET with high breakdown voltage and low on-resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US07476591B2
公开(公告)日：2009-01-13
申请号：US11581178
申请日：2006-10-13
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0878 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.
摘要翻译：提供具有高击穿电压和低导通电阻的半导体器件。一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。晶体管的源极和漏极区位于高压P阱和高压N阱中。可选地，在场电介质下的N阱区域中形成P场环。在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

55. 发明申请

US20090001462A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20090001462A1
公开(公告)日：2009-01-01
申请号：US12205961
申请日：2008-09-08
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

56. 发明授权

US09627524B2 High voltage metal oxide semiconductor device and method for making same 有权
公开(公告)号：US09627524B2
公开(公告)日：2017-04-18
申请号：US12715501
申请日：2010-03-02
申请人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
发明人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , H01L29/0847 , H01L29/1045 , H01L29/7833 , H01L29/7835
摘要： The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).

57. 发明授权

US09590049B2 Semiconductor composite film with heterojunction and manufacturing method thereof 有权
标题翻译：具有异质结的半导体复合膜及其制造方法
公开(公告)号：US09590049B2
公开(公告)日：2017-03-07
申请号：US14966818
申请日：2015-12-11
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L21/336 , H01L29/205 , H01L29/78 , H01L21/02 , H01L21/306 , H01L29/20 , H01L29/12
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

58. 发明授权

US09484437B2 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：横向双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US09484437B2
公开(公告)日：2016-11-01
申请号：US15018672
申请日：2016-02-08
申请人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
发明人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/762 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66681 , H01L21/76202 , H01L21/76224 , H01L21/76229 , H01L29/0649 , H01L29/0852 , H01L29/1095 , H01L29/6681 , H01L29/7816
摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
摘要翻译：本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件包括：漂移区，隔离氧化区，第一氧化物区，第二氧化物区，栅极，体区，源极和漏极。隔离氧化物区域，第一氧化物区域和第二氧化物区域分别具有隔离厚度，第一厚度和第二厚度，其中第二厚度小于第一厚度。本发明可以降低导通电阻而不降低第一氧化区和第二氧化区的LDMOS器件的击穿电压。

59. 发明申请

US20160099320A1 SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有异质性的半导体复合膜及其制造方法
公开(公告)号：US20160099320A1
公开(公告)日：2016-04-07
申请号：US14966818
申请日：2015-12-11
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/205 , H01L21/02 , H01L21/306 , H01L29/20
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

60. 发明授权

US09287394B2 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09287394B2
公开(公告)日：2016-03-15
申请号：US14510600
申请日：2014-10-09
申请人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
发明人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L21/762
CPC分类号： H01L29/66681 , H01L21/76202 , H01L21/76224 , H01L21/76229 , H01L29/0649 , H01L29/0852 , H01L29/1095 , H01L29/6681 , H01L29/7816
摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.

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