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    • 52. 发明申请
    • BUS ACCESS ARBITER AND METHOD OF BUS ARBITRATION
    • 总线访问ARBITER和总线仲裁方法
    • US20150067213A1
    • 2015-03-05
    • US14389410
    • 2012-12-27
    • Toshiki Takeuchi
    • Toshiki Takeuchi
    • G06F13/362G06F13/40
    • G06F13/362G06F13/4068
    • A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access.
    • 总线访问仲裁器包括访问模式判断单元和循环仲裁单元。 访问模式判断单元当从多个主站M0和M1生成总线访问时,判断连接的每个主站的访问模式是顺序访问模式还是单次访问模式。 循环仲裁单元根据访问模式动态切换用于仲裁总线访问的访问仲裁方法。 访问模式判断单元包括访问间隔计数单元,顺序访问次数计数单元和存储模式状态寄存器,其存储每个主设备的所判断的访问模式的状态,并且基于 访问间隔和顺序访问次数。
    • 53. 发明授权
    • Synchronization processing circuit and synchronization processing method in wireless communication system
    • 无线通信系统中的同步处理电路和同步处理方法
    • US08711902B2
    • 2014-04-29
    • US13144481
    • 2009-12-21
    • Toshiki Takeuchi
    • Toshiki Takeuchi
    • H04B1/00
    • H04B1/7095H04B1/70735H04B1/7075H04B1/7093H04B2201/70711
    • In a synchronization processing circuit in a wireless communication system, a correlation operation unit is designed to have a parallel structure which can be restructured to improve flexibility in order to cope with various synchronization processings in a plurality of radio systems.The synchronization processing circuit in the wireless communication system comprises a plurality of correlation operation modules 31 through 3N that execute correlation operation, each of which correlation operation modules includes a plurality of correlators 60, a plurality of shift registers 50 for shifting a correlation code, an interface which transfers a shifted correlation code to an adjacent correlation operation unit for timing correlation processing, and a correlation code selection unit 40 which selects an externally and individually applied correlation code for code correlation processing and a correlation code transferred from an adjacent correlation operation unit as the correlation code.
    • 在无线通信系统中的同步处理电路中,相关运算部被设计为具有可重构的并行结构,以提高灵活性,以应对多个无线电系统中的各种同步处理。 无线通信系统中的同步处理电路包括执行相关操作的多个相关运算模块31至3N,每个相关运算模块包括多个相关器60,用于移位相关码的多个移位寄存器50, 将相移代码转移到用于定时相关处理的相邻相关运算单元的接口,以及相关代码选择单元40,其选择用于代码相关处理的外部和单独应用的相关代码和从相邻相关运算单元传送的相关代码作为 相关代码。
    • 57. 发明授权
    • Data transfer device and data transfer method
    • 数据传输设备和数据传输方式
    • US08266467B2
    • 2012-09-11
    • US12669508
    • 2008-07-24
    • Toshiki Takeuchi
    • Toshiki Takeuchi
    • H04L7/00G06F13/42
    • G06F13/4291
    • To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A master (LSI1) outputs transfer data and a transfer synchronization clock signal to a slave (LSI2). For the edge of a clock signal used for data output at the master (LSI1), the slave (LSI2) latches input data by using a reverse edge. Moreover, upon data transfer from the slave (LSI2) to the master (LSI1), the master (LSI1) selects a latch timing of input data from a plurality of timings so that the transfer time to an internal circuit of the master (LSI1) side is identical regardless of which latch timing is selected.
    • 即使在评估板和实际装置之间的LSI之间的布线延迟变化时,也能够提供满足所需性能的传送吞吐量的LSI间数据同步传送,而不会导致整个系统的操作定时差异。 主机(LSI1)将传送数据和传送同步时钟信号输出到从机(LSI2)。 对于用于在主器件(LSI1)输出的数据的时钟信号的边沿,从器件(LSI2)通过使用反向边沿锁存输入数据。 此外,在从从机(LSI2)到主机(LSI1)的数据传送时,主机(LSI1)从多个定时中选择输入数据的锁存定时,使得到主机(LSI1)的内部电路的传送时间 无论选择哪个锁存定时,一侧是相同的。