专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20070096263A1 Accessible chip stack and process of manufacturing thereof 有权
标题翻译：无障碍芯片堆栈及其制造工艺
公开(公告)号：US20070096263A1
公开(公告)日：2007-05-03
申请号：US11266456
申请日：2005-11-03
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L29/40 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002
摘要： A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.
摘要翻译：制造三维集成电路芯片或晶片组件的过程，更具体地说，在将芯片定向成堆叠之前，将其布置在晶片上的处理。还公开了三维集成电路的制造，其中芯片密度可以非常高并且在晶片仍然完整且通常为平面结构的情况下被处理。

52. 发明申请

US20070025138A1 NON-VOLATILE SWITCHING AND MEMORY DEVICES USING VERTICAL NANOTUBES 有权
标题翻译：非挥发性开关和使用垂直纳米管的存储器件
公开(公告)号：US20070025138A1
公开(公告)日：2007-02-01
申请号：US11161183
申请日：2005-07-26
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , G11C2213/77 , Y10S977/742 , Y10S977/939 , Y10S977/943
摘要： Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.
摘要翻译：使用垂直纳米管的非易失性和辐射硬的开关和存储器件，并通过范德华力力可逆地保持状态和制造器件的方法。用于感测装置状态的装置包括测量电容，以及隧穿和场发射电流。

53. 发明申请

US20060228835A1 METHOD OF DOPING A GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR 失效
标题翻译：电场效应晶体管的栅极电极的方法
公开(公告)号：US20060228835A1
公开(公告)日：2006-10-12
申请号：US10907569
申请日：2005-04-06
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface ; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.
摘要翻译：一种制造结构并制造相关半导体晶体管和新型半导体晶体管结构的方法。制造该结构的方法包括：提供具有顶表面的基底; 在所述基板的顶表面上形成岛，所述岛的顶表面平行于所述基底的顶表面，所述岛的侧壁在所述岛的顶表面和所述基底的顶表面之间延伸; 在岛的侧壁上形成多个碳纳米管; 并且进行离子注入，所述离子注入在所述岛状体和所述碳纳米管所掩盖的基板的区域中贯穿所述岛并阻止其侵入所述基板。

54. 发明申请

US20060220148A1 Shallow trench isolation formation 有权
标题翻译：浅沟隔离形成
公开(公告)号：US20060220148A1
公开(公告)日：2006-10-05
申请号：US11445786
申请日：2006-06-02
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/76
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02282 , H01L21/3143 , H01L21/3147 , H01L21/316 , H01L21/76224 , H01L21/823878
摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.
摘要翻译：一种用于形成半导体结构的方法和结构。提供半导体衬底。在半导体衬底内形成沟槽。第一层电绝缘材料形成在沟槽内。去除第一层电绝缘材料的第一部分和第二部分。选择性地在第一层上生长第二层电绝缘材料，该第一层包括去除的第一部分和被去除的第二部分。

55. 发明申请

US20060202239A1 METHODS FOR PROVIDING GATE CONDUCTORS ON SEMICONDUCTORS AND SEMICONDUCTORS FORMED THEREBY 有权
标题翻译：提供其半导体栅极导体的方法及其形成的半导体
公开(公告)号：US20060202239A1
公开(公告)日：2006-09-14
申请号：US10906876
申请日：2005-03-10
申请人： Steven Holmes , Toshiharu Furukawa , Charles Koburger , David Horak , Mark Hakey
发明人： Steven Holmes , Toshiharu Furukawa , Charles Koburger , David Horak , Mark Hakey
IPC分类号： H01L29/772 , H01L21/8232
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the seed layer. The dummy gate defines a location for the gate conductor. Semiconductor devices having a dummy gate plated thereon to a width of between about 10 to about 70 nanometers are also provided.
摘要翻译：提供了一种在半导体上提供栅极导体的方法。该方法包括在半导体上限定有机聚合物电镀心轴，激活有机聚合物电镀心轴的一个或多个位置，将种子层结合到活化部位，以及在种子层上电镀虚拟栅极。虚拟门限定了栅极导体的位置。还提供了具有在其上镀覆大约10至大约70纳米宽度的虚拟栅极的半导体器件。

56. 发明申请

US20060160363A1 SHALLOW TRENCH ISOLATION FORMATION 失效
标题翻译：浅层分离形成
公开(公告)号：US20060160363A1
公开(公告)日：2006-07-20
申请号：US10905681
申请日：2005-01-17
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/302
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02282 , H01L21/3143 , H01L21/3147 , H01L21/316 , H01L21/76224 , H01L21/823878
摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.
摘要翻译：一种用于形成半导体结构的方法和结构。提供半导体衬底。在半导体衬底内形成沟槽。第一层电绝缘材料形成在沟槽内。去除第一层电绝缘材料的第一部分和第二部分。选择性地在第一层上生长第二层电绝缘材料，该第一层包括去除的第一部分和被去除的第二部分。

57. 发明申请

US20070184588A1 WRAP-AROUND GATE FIELD EFFECT TRANSISTOR 有权
标题翻译：封边栅场效应晶体管
公开(公告)号：US20070184588A1
公开(公告)日：2007-08-09
申请号：US11735075
申请日：2007-04-13
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/78645 , H01L29/78648
摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.
摘要翻译：形成具有环绕，垂直排列的双栅电极的场效应晶体管。从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。第二次回蚀将栅极导体材料的一部分移除第二距离。第一和第二距离之间的差异定义了最终设备的栅极长度。剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

58. 发明申请

US20060169972A1 VERTICAL CARBON NANOTUBE TRANSISTOR INTEGRATION 有权
标题翻译：垂直碳纳米管晶体管集成
公开(公告)号：US20060169972A1
公开(公告)日：2006-08-03
申请号：US10906016
申请日：2005-01-31
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
IPC分类号： H01L29/06
CPC分类号： H01L27/0688 , B82Y10/00 , H01L21/823412 , H01L21/823425 , H01L21/823487 , H01L27/0705 , H01L27/286 , H01L51/0048 , H01L51/057 , Y10S977/938
摘要： A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor. A method of forming the inventive hybrid semiconductor structure having at least one shared node between the vertical carbon nanotube transistor and the horizontal semiconductor device is also provided.
摘要翻译：提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。还提供了形成本发明的混合半导体结构的方法，该结构在竖直碳纳米管晶体管和水平半导体器件之间具有至少一个共享节点。

59. 发明申请

US20050087875A1 METHOD OF FORMING GAS DIELECTRIC WITH SUPPORT STRUCTURE 失效
标题翻译：用支持结构形成气体电介质的方法
公开(公告)号：US20050087875A1
公开(公告)日：2005-04-28
申请号：US10605766
申请日：2003-10-24
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit , James Slinkman
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit , James Slinkman
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wiring-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.
摘要翻译：在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。在布线层电介质中形成诸如通孔或互连的导电结构。然后形成连接到导电结构的支撑件，支撑件包括其下的区域。然后从该区域去除布线层电介质以形成气体电介质。

60. 发明申请

US20060008927A1 Dual gated finfet gain cell 有权
标题翻译：双门控finfet增益单元
公开(公告)号：US20060008927A1
公开(公告)日：2006-01-12
申请号：US11221118
申请日：2005-09-07
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.
摘要翻译：用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。第一栅电极与存储装置电耦合。第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。当门控时，电流的大小取决于存储设备存储的电量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式