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51. 发明授权

US08901676B2 Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage (Vb), a method of forming an LEDMOSFET, and a silicon-controlled rectifier (SCR) incorporating a complementary pair of LEDMOSFETs 有权
标题翻译：具有高漏极对体击穿电压（Vb）的横向延伸的漏极金属氧化物半导体场效应晶体管（LEDMOSFET），形成LEDMOSFET的方法和结合有互补对的LEDMOSFET的可控硅整流器
公开(公告)号：US08901676B2
公开(公告)日：2014-12-02
申请号：US13238414
申请日：2011-09-21
申请人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
发明人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
IPC分类号： H01L29/78 , H01L29/41 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/74
CPC分类号： H01L29/66681 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66704 , H01L29/66795 , H01L29/7436 , H01L29/7824 , H01L29/7825 , H01L29/785
摘要： Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.
摘要翻译：公开了具有高漏极对体击穿电压的横向延伸漏极，金属氧化物半导体，场效应晶体管（LEDMOSFET）的实施例。离散导电场（CF）板与漏极漂移区的相对侧相邻，每侧具有成角度的侧壁，使得漏极漂移区和CF板之间的区域沿着漏极漂移区的长度具有连续增加的宽度，沟道区到漏极区。 CF板可以包括与漏极漂移区相同的半导体主体内的多晶硅或金属结构或掺杂剂注入区。 CF板和漏极漂移区域之间的区域可以包括与漏极漂移区域相同的半导体本体内的锥形介质区域或者替代地，锥形耗尽区域。还公开了用于形成LEDMOSFET的方法的实施例和结合了这种LEDMOSFET的可控硅整流器（SCR）的实施例。

52. 发明授权

US08698244B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method 有权
标题翻译：绝缘体上硅（SOI）结构配置为减少谐波，设计结构和方法
公开(公告)号：US08698244B2
公开(公告)日：2014-04-15
申请号：US12634893
申请日：2009-12-10
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

53. 发明授权

US08471340B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure 有权
公开(公告)号：US08471340B2
公开(公告)日：2013-06-25
申请号：US12627343
申请日：2009-11-30
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L21/70
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

54. 发明授权

US08299547B2 Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates 有权
标题翻译：具有锥形电介质板的横向延伸漏极金属氧化物半导体场效应晶体管（LEDMOSFET）
公开(公告)号：US08299547B2
公开(公告)日：2012-10-30
申请号：US12983439
申请日：2011-01-03
申请人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
发明人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
IPC分类号： H01L21/336
CPC分类号： H01L29/7824 , G06F17/5063 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66681 , H01L29/66704 , H01L29/66795 , H01L29/7825 , H01L29/785
摘要： A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.
摘要翻译：具有高漏极对体击穿电压（Vb）的横向延伸漏极，金属氧化物半导体场效应晶体管（LEDMOSFET）在漏极漂移区域的相对侧上并入门结构延伸。延伸部是锥形的，使得每个延伸部和漂移区域之间的距离从邻近通道区域的一端线性地增加到与漏极区域相邻的另一端部。在一个实施例中，这些扩展可以垂直延伸通过围绕LEDMOSFET的隔离区域。在另一个实施例中，扩展可以位于隔离区域的顶部。在任一种情况下，扩展在漏极漂移内产生强大的基本均匀的水平电场分布。还公开了通过限定扩展的尺寸来形成具有特定Vb的LEDMOSFET的方法以及用于将LEDMOSFET设计为具有特定Vb的程序存储装置。

55. 发明申请

US20120104496A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED ELECTRICAL ISOLATION 有权
标题翻译：具有增强电隔离的SOI无线电频率开关
公开(公告)号：US20120104496A1
公开(公告)日：2012-05-03
申请号：US13345871
申请日：2012-01-09
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

56. 发明授权

US08026131B2 SOI radio frequency switch for reducing high frequency harmonics 有权
标题翻译：用于降低高频谐波的SOI射频开关
公开(公告)号：US08026131B2
公开(公告)日：2011-09-27
申请号：US12342488
申请日：2008-12-23
申请人： Alan B. Botula , Edward J. Nowak , James A. Slinkman
发明人： Alan B. Botula , Edward J. Nowak , James A. Slinkman
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76251 , H01L27/1203
摘要： First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. The first doped semiconductor regions and the second doped semiconductor regions are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6 V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drained through electrical contacts connected to the first and second doped semiconductor regions, thereby reducing of harmonic signals in the semiconductor devices above and enhancing the performance of the semiconductor devices as a radio-frequency (RF) switch.
摘要翻译：直接在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成具有与底部半导体层相同类型掺杂的第一掺杂半导体区域和具有相反类型掺杂的第二掺杂半导体区域。第一掺杂半导体区域和第二掺杂半导体区域以不足以由于少数载流子正向偏置注入底部半导体层而引起过大电流的电压而相对于底部半导体层电接地或正向偏置，即，电位差不超过0.6V至0.8V。通过顶部半导体层上的半导体器件中的电信号在感应电荷层中形成的电荷通过连接到第一和第二掺杂半导体区域的电触点排出，从而减少上述半导体器件中的谐波信号并增强性能的半导体器件作为射频（RF）开关。

57. 发明申请

US20110131542A1 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 有权
标题翻译：用于减少谐波的硅绝缘体（SOI）结构，设计结构和方法
公开(公告)号：US20110131542A1
公开(公告)日：2011-06-02
申请号：US12634893
申请日：2009-12-10
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： G06F17/50
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

58. 发明授权

US07883990B2 High resistivity SOI base wafer using thermally annealed substrate 有权
标题翻译：使用热退火基板的高电阻率SOI基底晶片
公开(公告)号：US07883990B2
公开(公告)日：2011-02-08
申请号：US11931371
申请日：2007-10-31
申请人： Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
发明人： Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
IPC分类号： H01L21/762 , H01L21/46
CPC分类号： H01L21/76254 , H01L21/76256 , H01L29/78603 , Y10T428/249921 , Y10T428/31504
摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.
摘要翻译：提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率（HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。

59. 发明授权

US07868423B2 Optimized device isolation 有权
标题翻译：优化设备隔离
公开(公告)号：US07868423B2
公开(公告)日：2011-01-11
申请号：US12269073
申请日：2008-11-12
申请人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St. Onge , James A. Slinkman
发明人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St. Onge , James A. Slinkman
IPC分类号： H01L21/02
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.
摘要翻译：用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。隔离MOSFET的n阱连接到深n波段区域。所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

60. 发明授权

US07826038B2 Method for adjusting lithographic mask flatness using thermally induced pellicle stress 有权
标题翻译：使用热诱导防护薄膜应力调整光刻胶片平整度的方法
公开(公告)号：US07826038B2
公开(公告)日：2010-11-02
申请号：US12029506
申请日：2008-02-12
申请人： Emily F. Gallagher , Louis M. Kindt , James A. Slinkman , Richard E. Wistron
发明人： Emily F. Gallagher , Louis M. Kindt , James A. Slinkman , Richard E. Wistron
IPC分类号： G03B27/62 , G03F9/00
CPC分类号： G03F1/64 , G03F1/60
摘要： A method for adjusting the flatness of a lithographic mask includes determining an initial mask flatness of the mask, determining an applied stress for bringing the mask to a desired mask flatness, and determining a mounting temperature of a pellicle frame to be mounted to the mask, the mounting temperature corresponding to the applied stress. The actual temperature of the pellicle frame is adjusted to the determined mounting temperature, and the pellicle frame is mounted to the mask at the mounting temperature.
摘要翻译：调整光刻掩模的平坦度的方法包括：确定掩模的初始掩模平坦度，确定施加的应力以使掩模达到期望的掩模平坦度，以及确定要安装到掩模的防护薄膜组件框架的安装温度，安装温度对应于施加的应力。防护薄膜组件框架的实际温度被调整到确定的安装温度，并且防护膜框架在安装温度下安装到掩模上。

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