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    • 56. 发明申请
    • Actuator, optical device having actuator, and actuator manufacturing method
    • 执行器,具有致动器的光学装置和致动器制造方法
    • US20060227553A1
    • 2006-10-12
    • US11348788
    • 2006-02-07
    • Tomoaki NakamuraMakoto Inoguchi
    • Tomoaki NakamuraMakoto Inoguchi
    • F21S8/00
    • G02B26/0841B81B3/0051B81B2201/033B81B2201/042
    • An actuator includes: a base section; an object having a body portion and a holding portion holding the body portion in a manner that the body portion is movable against the base section; a movable comb-tooth portion extending from the object side in a direction substantially perpendicular to a formation direction of the holding portion; and a fixed comb-tooth portion which extends from the base section in a direction substantially perpendicular to the formation direction of the holding portion and which is arranged at a position at which the fixed comb-tooth portion is engaged with but having a gap from the movable comb-tooth portion; the fixed comb-tooth portion being composed of a steady-voltage-receiving fixed comb tooth that steadily supplies a drive voltage and a variable-voltage-receiving fixed comb tooth that receives a controlled voltage.
    • 致动器包括:基部; 物体具有主体部分和保持部分,其保持主体部分,使得主体部分能够相对于基部移动; 从所述物体侧沿与所述保持部的形成方向大致垂直的方向延伸的可动梳齿部; 以及固定梳齿部,其从与所述保持部的形成方向大致正交的方向从所述基部延伸,并且所述固定梳齿部配置在所述固定梳齿部与所述固定梳齿部接合的位置, 活动梳齿部分; 固定梳齿部分由稳定地提供驱动电压的稳压接收固定梳齿和接收受控电压的可变电压接收固定梳齿构成。
    • 58. 发明授权
    • Processing unit for a computer and a computer system incorporating such a processing unit
    • 用于计算机的处理单元和包含这种处理单元的计算机系统
    • US06216236B1
    • 2001-04-10
    • US09188903
    • 1998-11-10
    • Takeshi MiyaoManabu AraokaTomoaki NakamuraMasayuki TanjiShigenori KanekoKoji MasuiSaburou IijimaNobuyasu KanekawaShinichiro KanekawaYoshiki KobayashiHiroaki FukumaruKatsunori Tagiri
    • Takeshi MiyaoManabu AraokaTomoaki NakamuraMasayuki TanjiShigenori KanekoKoji MasuiSaburou IijimaNobuyasu KanekawaShinichiro KanekawaYoshiki KobayashiHiroaki FukumaruKatsunori Tagiri
    • G06F1134
    • G06F11/187G06F11/1064G06F11/141G06F11/1604G06F11/1641G06F11/1666G06F11/1679G06F11/18G06F11/181G06F11/184G06F11/185G06F11/20G06F11/2007G06F11/2028G06F11/203G06F11/2035G06F11/2043G06F12/0833G11C29/74
    • A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
    • 计算机系统具有经由一个或多个系统总线(1-1,1-2)连接的多个处理单元(2-1,2-2,2-n)。 每个处理单元(2-1,2-2,2-n)在公共支撑板(PL)上具有三个或更多个处理器(20-1,20-2,20-3),并由公共时钟单元 1000)。 三个处理器(20-1,20-2,20-3)执行相同的操作,并且通过比较三个处理器(20-1,20-2,20-3)的操作来检测处理器(20-1,20-2,20-3)中的故障 (20-1,20-2,20-3)。 如果一个处理器(20-1,20-2,20-3)失败,则可以在处理单元的其他两个处理器(20-1,20-2,20-3)中继续操作(2-1,2 -2,2-n),至少暂时在更换整个处理单元(2-1,2-2,2-n)之前。 此外,处理单元(2-1,2-2,2-n)可以在时钟单元(1000)内具有多个时钟(A,B),具有切换装置,使得处理器(20-1, 20-2,20-n)通常从主时钟(A)接收时钟脉冲,但是如果主时钟(A)发生故障,则从辅助时钟(B)接收脉冲。 在主时钟和辅助时钟(A,B)之间切换涉及从时钟(A,B)的脉冲持续时间的比较。 另外,多个高速缓冲存储器(220,221)可以共同地连接到处理器(20-1,20-2,20-3),使得一个高速缓冲存储器(220,221)的故障允许处理单元(2-1 ,2
    • 60. 发明授权
    • Floppy disk apparatus which adjusts gain conforming to operation of
carriage
    • 调整符合运输操作的增益的软盘装置
    • US5680270A
    • 1997-10-21
    • US616892
    • 1996-03-18
    • Tomoaki Nakamura
    • Tomoaki Nakamura
    • G11B21/10G11B5/596
    • G11B5/59622
    • The invention provides a floppy disk apparatus which can perform, where a carriage motor which makes a non-linear operation such as a linear stepping motor is employed, suitable gain adjustment conforming to operation of a carriage. Upon setting of a correction gain, the position of a magnetic head on a floppy disk medium is fixed by a main control section, and in this condition, servo information is read out from the floppy disk medium. From the servo information read out by the magnetic head, a tracking error signal is produced by a tracking error production section. Based on the thus produced tracking error signal, an operation amount calculation section calculates an operation amount of the carriage for one rotation of the floppy disk medium. A correction gain setting section calculates a correction gain based on the operation amount calculated by the operation amount calculation section, and sets the thus calculated correction gain to an operation amount correction section.
    • 本发明提供了一种软盘设备,其可以执行使诸如线性步进电机之类的非线性操作的滑架电动机,其适合于支架的操作的增益调节。 在设定校正增益时,通过主控制部分固定磁盘介质上的磁头的位置,在该状态下,从软盘介质读出伺服信息。 根据由磁头读出的伺服信息,跟踪误差产生部产生跟踪误差信号。 基于由此产生的跟踪误差信号,操作量计算部分计算软盘介质的一次旋转的滑架的操作量。 校正增益设定部根据由运算量计算部计算出的运算量来计算校正增益,并将这样计算出的校正增益设定为运算量校正部。