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51. 发明申请

US20130200521A1 INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL 有权
标题翻译：电感和接线结构与有限的材料制成
公开(公告)号：US20130200521A1
公开(公告)日：2013-08-08
申请号：US13367895
申请日：2012-02-07
申请人： Hanyi Ding , Jeffrey P. Gambino , Zhong-Xiang He , Alvin J. Joseph , Anthony K. Stamper , Timothy D. Sullivan
发明人： Hanyi Ding , Jeffrey P. Gambino , Zhong-Xiang He , Alvin J. Joseph , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L23/5227 , H01L23/5283 , H01L23/53223 , H01L23/645 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.
摘要翻译：后端（BEOL）布线结构和电感器，BEOL布线结构和电感器的制造方法以及BEOL布线结构或电感器的设计结构。形成可以是沟槽或导线的特征，其包括与电介质层的顶表面相交的侧壁。表面层形成在特征的侧壁上。表面层由导体构成，其厚度被选择为提供用于传导高频信号的低电阻路径。

52. 发明授权

US08569888B2 Wiring structure and method of forming the structure 有权
标题翻译：布线结构及形成方法
公开(公告)号：US08569888B2
公开(公告)日：2013-10-29
申请号：US13114079
申请日：2011-05-24
申请人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译：公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。较厚的上部位于布线结构和相邻电介质材料之间的接合处。较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

53. 发明授权

US07500208B2 Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime 有权
标题翻译：在深亚微米体系的半导体集成电路中的导电线的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US07500208B2
公开(公告)日：2009-03-03
申请号：US11673369
申请日：2007-02-09
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有部分的电阻来确定第一行几何调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

54. 发明授权

US08900964B2 Inductors and wiring structures fabricated with limited wiring material 有权
标题翻译：用有限布线材料制成的电感器和布线结构
公开(公告)号：US08900964B2
公开(公告)日：2014-12-02
申请号：US13367895
申请日：2012-02-07
申请人： Hanyi Ding , Jeffrey P. Gambino , Zhong-Xiang He , Alvin J. Joseph , Anthony K. Stamper , Timothy D. Sullivan
发明人： Hanyi Ding , Jeffrey P. Gambino , Zhong-Xiang He , Alvin J. Joseph , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L21/20 , H01L27/08
CPC分类号： H01L23/5227 , H01L23/5283 , H01L23/53223 , H01L23/645 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.
摘要翻译：后端（BEOL）布线结构和电感器，BEOL布线结构和电感器的制造方法以及BEOL布线结构或电感器的设计结构。形成可以是沟槽或导线的特征，其包括与电介质层的顶表面相交的侧壁。表面层形成在特征的侧壁上。表面层由导体构成，其厚度被选择为提供用于传导高频信号的低电阻路径。

55. 发明授权

US07445966B2 Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
标题翻译：集成电路制造期间电荷耗散的方法和结构及其分离
公开(公告)号：US07445966B2
公开(公告)日：2008-11-04
申请号：US11160468
申请日：2005-06-24
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Timothy D. Sullivan , Steven H. Voldman
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Timothy D. Sullivan , Steven H. Voldman
IPC分类号： H01L23/60
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

56. 发明授权

US08652922B2 Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture 有权
标题翻译：紧凑的热控薄膜电阻器，利用基板触点和制造方法
公开(公告)号：US08652922B2
公开(公告)日：2014-02-18
申请号：US13008459
申请日：2011-01-18
申请人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
发明人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L27/0207 , H01L27/1203
摘要： A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.
摘要翻译：形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并在电阻器中形成沟槽并进入衬底。该方法还包括在沟槽的侧壁上形成衬垫，并在沟槽和衬垫上形成包括高导热性材料的芯。

57. 发明授权

US08647909B2 Array of alpha particle sensors 失效
标题翻译： α粒子传感器阵列
公开(公告)号：US08647909B2
公开(公告)日：2014-02-11
申请号：US13357728
申请日：2012-01-25
申请人： Ethan H. Cannon , Michael J. Hauser , Timothy D. Sullivan
发明人： Ethan H. Cannon , Michael J. Hauser , Timothy D. Sullivan
IPC分类号： H01L21/00
CPC分类号： H01L31/115 , H01L23/552 , H01L23/556 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).
摘要翻译：辐射传感器或检测器阵列集成在三维半导体IC内。传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。

58. 发明授权

US08480302B2 Micro-electro-mechanical-system temperature sensor 失效
标题翻译：微机电系统温度传感器
公开(公告)号：US08480302B2
公开(公告)日：2013-07-09
申请号：US12892406
申请日：2010-09-28
申请人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
发明人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
IPC分类号： G01K5/00 , G01K7/00
CPC分类号： G01K5/52
摘要： The present invention provides a micro-electro-mechanical-system (MEMS) temperature sensor that employs a suspended spiral comprising a material with a positive coefficient of thermal expansion. The thermal expansion of the suspended spiral is guided to by a set of guideposts to provide a linear movement of the free end of the suspended spiral, which is converted to an electrical signal by a set of conductive rotor azimuthal fins that are interdigitated with a set of conductive stator azimuthal fins by measuring the amount of capacitive coupling therebetween. Real time temperature may thus be measured through the in-situ measurement of the capacitive coupling. Optionally, the MEMS temperature sensor may have a ratchet and a pawl to enable ex-situ measurement.
摘要翻译：本发明提供了一种微电子机械系统（MEMS）温度传感器，其采用悬浮螺旋，其包括具有正的热膨胀系数的材料。悬挂螺旋的热膨胀由一组导轨引导以提供悬挂螺旋的自由端的线性运动，其被一组导电转子方位角翅片转换成电信号，所述导电转子方位角翅片与组相互指向通过测量导电定子方位翅片之间的电容耦合量。因此可以通过电容耦合的原位测量来测量实时温度。可选地，MEMS温度传感器可以具有棘轮和棘爪以使得能够进行非原位测量。

59. 发明授权

US08018017B2 Thermo-mechanical cleavable structure 有权
标题翻译：热机械可切割结构
公开(公告)号：US08018017B2
公开(公告)日：2011-09-13
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
发明人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
IPC分类号： H01L31/058
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

60. 发明授权

US07868453B2 Solder interconnect pads with current spreading layers 有权
标题翻译：具有电流扩散层的焊料互连焊盘
公开(公告)号：US07868453B2
公开(公告)日：2011-01-11
申请号：US12032158
申请日：2008-02-15
申请人： Timothy Harrison Daubenspeck , Timothy D. Sullivan
发明人： Timothy Harrison Daubenspeck , Timothy D. Sullivan
IPC分类号： H01L23/52
CPC分类号： H01L23/488 , H01L24/05 , H01L24/13 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05541 , H01L2224/05557 , H01L2224/05572 , H01L2224/05624 , H01L2224/13007 , H01L2224/13099 , H01L2224/16 , H01L2224/45147 , H01L2224/48824 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/207 , H01L2924/00 , H01L2224/05552
摘要： Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.
摘要翻译：制作结构的结构和方法。所述结构包括结构，包括：在衬底上延伸的有机介电钝化层; 在所述有机介电钝化层的顶表面上的导电电流扩散焊盘; 导电焊料凸块焊盘，其在电流扩散焊盘的顶表面上包括一层或多层; 以及包含锡的导电焊料凸块，所述焊料凸块在所述焊料凸块焊盘的顶表面上，所述电流扩散焊盘包括一个或多个层，所述一个或多个层中的至少一个由不会形成金属间化合物与锡或一层或多层中的至少一层是对锡的扩散阻挡层并且与焊料凸块相邻的材料。

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