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51. 发明申请

US20090307470A1 MULTI THREAD PROCESSOR HAVING DYNAMIC RECONFIGURATION LOGIC CIRCUIT 有权
标题翻译：具有动态重构逻辑电路的多线程处理器
公开(公告)号：US20090307470A1
公开(公告)日：2009-12-10
申请号：US12093884
申请日：2006-11-21
申请人： Masaki Maeda , Hideshi Nishida , Yorihiko Wakayama
发明人： Masaki Maeda , Hideshi Nishida , Yorihiko Wakayama
IPC分类号： G06F9/318
CPC分类号： G06F15/7867
摘要： A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and causes concurrent execution of an operation cell having a configuration for the current thread and (ii) an operation cell having a configuration for the next thread.
摘要翻译：根据本发明的处理器在分配给它的每个时间段周期性地执行多个线程。处理器为每个线程存储操作单元的配置信息。每个线程使得执行不同的预定数量的操作单元串联，并且在分配给当前线程的时间段内，基于存储的一条配置信息，连续地重新配置已经完成其最后操作的操作单元对应于下一个线程的操作单元，并且使具有当前线程的配置的操作单元并行执行，以及（ii）具有下一个线程的配置的操作单元。

52. 发明申请

US20080307198A1 SIGNAL-PROCESSING APPARATUS AND ELECTRONIC APPARATUS USING SAME 审中-公开
标题翻译：信号处理装置和使用它的电子装置
公开(公告)号：US20080307198A1
公开(公告)日：2008-12-11
申请号：US12179873
申请日：2008-07-25
申请人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
发明人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： H04N19/86 , G06F9/3885 , H04N19/42 , H04N19/436 , H04N19/44 , H04N19/523 , H04N19/61
摘要： A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.
摘要翻译：信号处理装置包括指令并行处理器，第一数据并行处理器，第二数据并行处理器和运动检测单元，解块滤波单元和可变长度编码/解码单元，它们是专用的硬件。利用这种结构，在需要大量处理的图像压缩和解压缩算法的信号处理期间，负载分布在软件和硬件之间，使得信号处理装置可以实现高处理能力和灵活性。

53. 发明申请

US20080247461A1 Image Encoding Device 有权
标题翻译：图像编码装置
公开(公告)号：US20080247461A1
公开(公告)日：2008-10-09
申请号：US11662783
申请日：2005-09-05
申请人： Hideshi Nishida
发明人： Hideshi Nishida
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/58 , H04N19/127 , H04N19/137 , H04N19/157 , H04N19/172 , H04N19/51 , H04N19/57 , H04N19/61
摘要： In an image encoding device (100) that compression encodes moving pictures, a moving picture count acquisition unit (110) acquires a moving picture count of encoding target moving pictures corresponding to an arbitrary number of input moving pictures, a moving picture acquisition unit (120) acquires one or plural encoding target moving pictures, a processing method designation unit (130), in accordance with the acquired count, designates processing methods relating to encoding processing that affect a computation amount, for example, processing methods relating to a reference image frame count upper limit or a motion vector range, such that the greater the moving picture count is, the smaller the computation amount is, and an encoding processing unit (140) performs encoding processing with respect to the acquired one or plural moving pictures, using time division when the plural moving pictures are plural. The encoding unit (140) performs encoding processing using the designated methods.
摘要翻译：在对运动图像进行压缩编码的图像编码装置（100）中，运动图像计数获取部（110）获取与任意数量的输入运动图像对应的编码目标运动图像的运动图像数，运动图像获取部）获取一个或多个编码对象运动图像，根据获取的计数，处理方法指定单元（130）指定与影响计算量的编码处理相关的处理方法，例如，与参考图像帧有关的处理方法计数上限或运动矢量范围，使得运动图像数量越大计算量越小，并且编码处理单元（140）使用时间对所获取的一个或多个运动图像执行编码处理当多个运动图像是多个时分割。编码单元（140）使用指定的方法进行编码处理。

54. 发明申请

US20080209162A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
公开(公告)号：US20080209162A1
公开(公告)日：2008-08-28
申请号：US12110491
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

55. 发明授权

US07020787B2 Microprocessor 失效
公开(公告)号：US07020787B2
公开(公告)日：2006-03-28
申请号：US10323419
申请日：2002-12-18
申请人： Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
发明人： Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F7/57
摘要： A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

56. 发明申请

US20050238095A1 Transcoder 失效
标题翻译：转码器
公开(公告)号：US20050238095A1
公开(公告)日：2005-10-27
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： G06T3/40 , H04N7/12 , H04N7/26 , H04N7/46 , H04N7/50
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

57. 发明授权

US06414608B1 Variable length code decoding device, digital broadcast receiving apparatus, and DVD reproducing apparatus 有权
标题翻译：可变长码解码装置，数字广播接收装置和DVD再现装置
公开(公告)号：US06414608B1
公开(公告)日：2002-07-02
申请号：US09583374
申请日：2000-05-31
申请人： Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： H03M740
CPC分类号： H04N19/436 , H04N19/61 , H04N19/91
摘要： A first bit string extracting unit extracts a first bit string. A first bit length judging unit detects a first codeword from the first bit string. A first decoding unit generates a first run-level pair from the first codeword. A second bit string extracting unit extracts a second bit string. A second bit length judging unit detects a second codeword from the second bit string. A second decoding unit generates a second run-level pair from the second codeword. A first inverse quantizing unit inverse quantizes the first level to obtain a DCT coefficient. A second inverse quantizing unit inverse quantizes the second level to obtain a DCT coefficient. A second buffer controller writes the DCT coefficients and their first buffer addresses into a second buffer. A first buffer controller reads the DCT coefficients and the first buffer addresses from the second buffer and writes the DCT coefficients into a first buffer at the respective first buffer addresses.
摘要翻译：第一位串提取单元提取第一位串。第一比特长度判断单元从第一比特串检测第一码字。第一解码单元从第一码字生成第一游程级对。第二位串提取单元提取第二位串。第二位长度判断单元从第二位串检测第二码字。第二解码单元从第二码字生成第二游程级对。第一反量化单元逆量化第一电平以获得DCT系数。第二反量化单元逆量化第二电平以获得DCT系数。第二缓冲器控制器将DCT系数及其第一缓冲器地址写入第二缓冲器。第一缓冲器控制器从第二缓冲器读取DCT系数和第一缓冲器地址，并将DCT系数写入相应的第一缓冲器地址的第一缓冲器。

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