专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06839288B1 Latch scheme with invalid command detector 有权
标题翻译：具有无效命令检测器的锁存方案
公开(公告)号：US06839288B1
公开(公告)日：2005-01-04
申请号：US10706146
申请日：2003-11-12
申请人： Jung Pill Kim , Jonghee Han , Stephen Camacho
发明人： Jung Pill Kim , Jonghee Han , Stephen Camacho
IPC分类号： G11C7/10 , G11C8/06 , G11C8/18 , G11C8/20 , G11C11/408 , G11C11/4093 , G11C7/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C11/4082 , G11C11/4093
摘要： Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced by preventing the outputs of the latch circuits from changing when an invalid command is detected. For some embodiments, an invalid command detector is provided that generates an invalid command signal used to inhibit latch circuits, in response to detecting an invalid command.
摘要翻译：提供了用于减少对锁存电路的输出的不必要的改变的方法和电路。当检测到无效命令时，可以通过防止锁存电路的输出改变来减少锁存电路的输出的不必要的改变。对于一些实施例，提供无效命令检测器，其响应于检测到无效命令而产生用于禁止锁存电路的无效命令信号。

52. 发明授权

US06774691B2 High resolution interleaved delay chain 有权
标题翻译：高分辨率交错延迟链
公开(公告)号：US06774691B2
公开(公告)日：2004-08-10
申请号：US10337606
申请日：2003-01-07
申请人： Jonghee Han , Jung Pill Kim
发明人： Jonghee Han , Jung Pill Kim
IPC分类号： H03L706
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058
摘要： An improved delay chain for use in a delay locked loop which provides smooth phase adjustment and high resolution. In a delay chain having a series of cascaded unit delay elements, the outputs of a pair of contiguous delay elements (N, N+1) are selected for input to a phase blender. A coarse delay adjustment is carried out by selecting the outputs of the next pair of contiguous delay elements (N+1, N+2) and thus affects only one of the phase blender inputs. The phase blender provides a fine delay adjustment by generating an output whose phase is a weighted combination of the inputs, the weights having an inverse relationship. A coarse delay adjustment which affects an input of the phase blender is carried out when the weighting of that input is zero. Fine-to-coarse hand-over problems which characterize known delay locked loops are thus avoided.
摘要翻译：用于延迟锁定环的改进的延迟链，其提供平滑的相位调整和高分辨率。在具有一系列级联单元延迟元件的延迟链中，选择一对连续延迟元件（N，N + 1）的输出用于输入到相位混合器。通过选择下一对连续延迟元件（N + 1，N + 2）的输出来执行粗略延迟调整，因此仅影响一个相位搅拌器输入。相位混合器通过产生其相位是输入的加权组合的输出来提供精细的延迟调整，权重具有反比关系。当该输入的加权为零时，执行影响相位混合器的输入的粗略延迟调整。因此避免了表征已知延迟锁定环的细到粗移交问题。

53. 发明授权

US07193883B2 Input return path based on Vddq/Vssq 有权
标题翻译：基于Vddq / Vssq的输入返回路径
公开(公告)号：US07193883B2
公开(公告)日：2007-03-20
申请号：US10870100
申请日：2004-06-17
申请人： Jonghee Han
发明人： Jonghee Han
IPC分类号： G11C11/24
CPC分类号： G11C5/14
摘要： Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same are provided. Input signal return path noise may be decoupled from the power for receiver circuits, for example, by utilizing separate power supply lines, such as VDDQ and VSSQ, as input signal return path.
摘要翻译：提供了减少由公共输入信号返回路径引起的输入信号抖动量的输入电路配置，使用其的方法和电路。输入信号返回路径噪声可以与接收机电路的功率分离，例如通过使用诸如V DDQ和V SSQ之类的单独电源线作为输入信号返回路径。

54. 发明授权

US07123524B1 Input circuit having updated output signal synchronized to clock signal 失效
标题翻译：具有与时钟信号同步的更新的输出信号的输入电路
公开(公告)号：US07123524B1
公开(公告)日：2006-10-17
申请号：US11128688
申请日：2005-05-13
申请人： Jonghee Han
发明人： Jonghee Han
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/1093
摘要： An input circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal and a second signal and to sample the first signal via the second signal and provide signal samples of the first signal. The second circuit is configured to receive a third signal and the signal samples and to update a second circuit output signal via the third signal and provide the updated second circuit output signal. The third circuit is configured to receive a clock signal and the second signal and to provide the third signal. The third circuit is also configured to synchronize edges in the third signal to edges in the second signal and edges in the clock signal.
摘要翻译：一种包括第一电路，第二电路和第三电路的输入电路。第一电路被配置为接收第一信号和第二信号，并且经由第二信号对第一信号进行采样并提供第一信号的信号采样。第二电路被配置为接收第三信号并且信号采样并且经由第三信号更新第二电路输出信号并提供更新的第二电路输出信号。第三电路被配置为接收时钟信号和第二信号并提供第三信号。第三电路还被配置为将第三信号中的边沿与第二信号中的边沿和时钟信号中的边沿同步。

55. 发明申请

US20060214714A1 Duty cycle corrector 有权
标题翻译：占空比校正器
公开(公告)号：US20060214714A1
公开(公告)日：2006-09-28
申请号：US11442842
申请日：2006-05-30
申请人： Joonho Kim , Jung Kim , Jonghee Han
发明人： Joonho Kim , Jung Kim , Jonghee Han
IPC分类号： H03K3/017
CPC分类号： G06F1/04 , H03K5/1565
摘要： A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.
摘要翻译：公开了包括第一，第二电路和第三电路的占空比校正器。第三电路被配置为响应于由第一电路和第二电路调节的电荷流量获得阈值，其中第一电路被配置为接收时钟信号并且在时钟的第一转变处改变电荷流信号。第二电路被配置为在时钟信号的第二转变处改变电荷流。第一电路和第二电路被配置为响应于获得阈值来改变电荷流。

56. 发明申请

US20060152265A1 Duty cycle corrector 有权
标题翻译：占空比校正器
公开(公告)号：US20060152265A1
公开(公告)日：2006-07-13
申请号：US11032459
申请日：2005-01-10
申请人： Joonho Kim , Jung Kim , Jonghee Han
发明人： Joonho Kim , Jung Kim , Jonghee Han
IPC分类号： H03K3/017
CPC分类号： G06F1/04 , H03K5/1565
摘要： A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.
摘要翻译：一种占空比校正器，包括第一电路和第二电路。第一电路被配置为接收具有第一相位和第二相位的时钟信号，并且基于第一相位的长度和第二相位的一部分来获得第一阈值，并且提供第一脉冲和对第一阈值的响应值。第二电路被配置为接收时钟信号并且基于第二相位的长度和第一相的一部分获得第二阈值，并且响应于第二阈值提供第二脉冲。第一脉冲的开始和第二脉冲的开始之间的时间基本上是一个半个时钟周期。

57. 发明授权

US07031205B2 Random access memory with post-amble data strobe signal noise rejection 失效
标题翻译：具有后同步数据选通信号噪声抑制的随机存取存储器
公开(公告)号：US07031205B2
公开(公告)日：2006-04-18
申请号：US10674177
申请日：2003-09-29
申请人： Jonghee Han , Alexander George , Torsten Partsch
发明人： Jonghee Han , Alexander George , Torsten Partsch
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A random access memory includes a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal, and a second circuit configured to receive the strobe signal to latch data into the second circuit in response to the strobe signal, and to receive the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal. The first circuit includes an enable circuit configured to provide an enable signal and a buffer circuit configured to receive the strobe signal and the enable signal and provide the pulses in response to the enable signal and the strobe signal. The enable circuit is configured to receive the pulses from the buffer circuit and stop providing the enable signal to the buffer circuit in response to receiving the pulses.
摘要翻译：随机存取存储器包括被配置为接收选通信号并响应于选通信号中的转换提供脉冲的第一电路，以及被配置为接收选通信号以响应于选通信号将数据锁存到第二电路中的第二电路，并且在选通信号中的转换之后接收脉冲以将锁存的数据重新锁存到第二电路中。第一电路包括使能电路，其被配置为提供使能信号和缓冲电路，其被配置为接收选通信号和使能信号，并响应于使能信号和选通信号提供脉冲。使能电路被配置为从缓冲电路接收脉冲，并且响应于接收脉冲而停止向缓冲电路提供使能信号。

58. 发明申请

US20050068810A1 Random access memory with post-amble data strobe signal noise rejection 失效
标题翻译：具有后同步数据选通信号噪声抑制的随机存取存储器
公开(公告)号：US20050068810A1
公开(公告)日：2005-03-31
申请号：US10674177
申请日：2003-09-29
申请人： Jonghee Han , Alexander George , Torsten Partsch
发明人： Jonghee Han , Alexander George , Torsten Partsch
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A random access memory comprises a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal. The random access memory comprises a second circuit configured to receive the strobe signal to latch data into the second circuit, and to receive the pulses to latch the latched data into the second circuit after the transitions in the strobe signal.
摘要翻译：随机存取存储器包括被配置为接收选通信号并响应于选通信号中的转变提供脉冲的第一电路。随机存取存储器包括第二电路，其被配置为接收选通信号以将数据锁存到第二电路中，并且在选通信号中的转换之后接收脉冲以将锁存的数据锁存到第二电路中。

59. 发明授权

US06847566B1 Method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device 失效
标题翻译：用于在DRAM器件中的刷新操作期间进行多次充电回收的方法和电路配置
公开(公告)号：US06847566B1
公开(公告)日：2005-01-25
申请号：US10692119
申请日：2003-10-23
申请人： Jonghee Han , Jung Pill Kim
发明人： Jonghee Han , Jung Pill Kim
IPC分类号： G11C5/06 , G11C7/06 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/06 , G11C11/406 , G11C11/4074 , G11C2207/065
摘要： Methods and circuit configurations for multiple recycling of charge during a refresh operation in a memory device, such as a dynamic random access memory (DRAM) device, are provided. Charge from one or more power lines of a first array of bit line sense amplifiers involved in a first refresh operation may be transferred to one or more power lines of at least second and third arrays of bit line sense amplifiers involved in subsequent refresh operations.
摘要翻译：提供了在诸如动态随机存取存储器（DRAM）设备的存储器件中的刷新操作期间多次再循环电荷的方法和电路配置。可以将涉及第一刷新操作的位线读出放大器的第一阵列的一个或多个电源线的电荷传送到后续刷新操作中涉及的位线读出放大器的至少第二和第三阵列的一个或多个电力线。

60. 发明授权

US07420399B2 Duty cycle corrector 有权
标题翻译：占空比校正器
公开(公告)号：US07420399B2
公开(公告)日：2008-09-02
申请号：US11271015
申请日：2005-11-10
申请人： Jonghee Han
发明人： Jonghee Han
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565 , H03L7/0805 , H03L7/0812
摘要： A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal, and a phase mixer configured to phase mix the first signal and the third signal to provide a fourth signal.
摘要翻译：占空比校正器包括被配置为延迟第一信号以提供第二信号的第一可控延迟，被配置为延迟第二信号以提供第三信号的第二可控延迟，被配置为调整第一可控延迟和第二可控延迟的电路延迟相位锁定第三信号到第一信号，以及相位混频器，被配置为相位混合第一信号和第三信号以提供第四信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式