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51. 发明申请

US20140019723A1 BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：不对称多处理器系统中的二进制翻译
公开(公告)号：US20140019723A1
公开(公告)日：2014-01-16
申请号：US13993042
申请日：2011-12-28
申请人： Koichi Yamada , Ronny Ronen , Wei Li , Boris Ginzburg , Gadi Haber , Konstantin Levit-Gurevich , Esfir Natanzon , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
发明人： Koichi Yamada , Ronny Ronen , Wei Li , Boris Ginzburg , Gadi Haber , Konstantin Levit-Gurevich , Esfir Natanzon , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F1/3243 , G06F1/3293 , G06F9/30174 , G06F9/3808 , G06F9/4552 , G06F9/5094 , G06F15/7807 , Y02D10/122 , Y02D10/152 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。分析用于在ASMP上执行的程序代码，并且确定是否允许程序代码或其代码段在本地上在第一核上执行或者对代码使用二进制转换并且在在执行过程中消耗的功率比第一个核心少的第二个核心。

52. 发明申请

US20120233439A1 Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices 审中-公开
标题翻译：在处理设备之间实现具有共享虚拟内存的系统的TLB同步
公开(公告)号：US20120233439A1
公开(公告)日：2012-09-13
申请号：US13045688
申请日：2011-03-11
申请人： Boris Ginzburg , Esfir Natanzon , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Yoav Zach , Robert L. Farrell
发明人： Boris Ginzburg , Esfir Natanzon , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Yoav Zach , Robert L. Farrell
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1036 , G06F12/109 , G06F2212/302 , G06F2212/682
摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.
摘要翻译：在图形处理单元中出现的页面错误可以由在中央处理单元上运行的操作系统来处理。在一些实施例中，这意味着未被固定的存储器可以用于图形处理单元。在图形处理单元中使用未固定的存储器可以在某些情况下扩展图形处理单元的能力。

53. 发明申请

US20100115304A1 POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES 有权
标题翻译：多处理器电源的电源管理
公开(公告)号：US20100115304A1
公开(公告)日：2010-05-06
申请号：US12263421
申请日：2008-10-31
申请人： Lev Finkelstein , Efraim Rotem , Aviad Cohen , Ronny Ronen , Doron Rajwan
发明人： Lev Finkelstein , Efraim Rotem , Aviad Cohen , Ronny Ronen , Doron Rajwan
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/26 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.
摘要翻译：描述与多个处理器核心的电源管理相关的方法和装置。在一个实施例中，本地可以利用一个或多个技术（例如，基于每个核心）来管理处理器中的功率消耗。在另一个实施例中，功率可以基于能量考虑而分布在处理器的不同功率层之间。还公开并要求保护其他实施例。

54. 发明授权

US07437581B2 Method and apparatus for varying energy per instruction according to the amount of available parallelism 有权
标题翻译：根据可用的并行度量来改变每个指令的能量的方法和装置
公开(公告)号：US07437581B2
公开(公告)日：2008-10-14
申请号：US10952627
申请日：2004-09-28
申请人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad S Sheaffer , Ronny Ronen , Murali M. Annavaram
发明人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad S Sheaffer , Ronny Ronen , Murali M. Annavaram
IPC分类号： G06F1/32 , G06F9/46
CPC分类号： G06F9/3851 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/3885 , G06F9/3891 , G06F9/3897 , Y02D10/16 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.
摘要翻译：公开了一种用于改变多核处理器的配置的方法和装置。在一个实施例中，节气门模块（或节气门逻辑）可以确定当前执行的程序中存在的并行度量，并且改变该程序在各种核心上的线程的执行。如果并行量高，则处理器可以被配置为在被配置为消耗较少功率的核上运行更大量的线程。如果并行量较低，则处理器可能被配置为在配置为更高标量性能的核心上运行较少量的线程。

55. 发明授权

US07159133B2 Low-power processor hint, such as from a pause instruction 有权
标题翻译：低功耗处理器提示，例如从暂停指令
公开(公告)号：US07159133B2
公开(公告)日：2007-01-02
申请号：US10759455
申请日：2004-01-16
申请人： Doron Orenstien , Ronny Ronen
发明人： Doron Orenstien , Ronny Ronen
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , G06F9/30083 , G06F9/3009 , G06F9/30189 , G06F9/3836 , G06F9/3851 , Y02D10/126 , Y02D10/172
摘要： A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.
摘要翻译：系统和相应的方法使用“处理器慢速模式”在单个线程或多线程环境中使用PAUSE指令作为低功耗提示。一个实施例实际上降低了处理器时钟的频率。另外一个实施例通过在N个时钟周期内门控M个时钟周期来实际上降低处理器时钟的频率。当所有线程发出PAUSE指令时，处理器进入慢速模式并保持一段时间。此后，处理器返回正常模式。或者，诸如中断或异常的事件可以使处理器从慢速模式返回正常模式。

56. 发明申请

US20060053245A1 Power reduction for processor front-end by caching decoded instructions 有权
公开(公告)号：US20060053245A1
公开(公告)日：2006-03-09
申请号：US11217474
申请日：2005-09-02
申请人： Baruch Solomon , Ronny Ronen , Doron Orenstien
发明人： Baruch Solomon , Ronny Ronen , Doron Orenstien
IPC分类号： G06F12/00
CPC分类号： G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
摘要： A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.

57. 发明申请

US20050050373A1 Distribution of processing activity in a multiple core microprocessor 有权
标题翻译：在多核微处理器中处理活动的分布
公开(公告)号：US20050050373A1
公开(公告)日：2005-03-03
申请号：US10964413
申请日：2004-10-12
申请人： Doron Orenstien , Ronny Ronen
发明人： Doron Orenstien , Ronny Ronen
IPC分类号： G06F1/20 , G06F1/32 , G06F1/30
CPC分类号： G06F9/4856 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
摘要翻译：基于功耗和/或热考虑分布处理硬件的处理活动。一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。

58. 发明授权

US06697933B1 Method and apparatus for fast, speculative floating point register renaming 有权
标题翻译：用于快速，推测浮点寄存器重命名的方法和装置
公开(公告)号：US06697933B1
公开(公告)日：2004-02-24
申请号：US09539221
申请日：2000-03-30
申请人： Gregory Pribush , Ronny Ronen , Bishara Shomar
发明人： Gregory Pribush , Ronny Ronen , Bishara Shomar
IPC分类号： G06F930
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： According to one aspect of the invention, a method is provided in which a current instance of an instruction is received. The current instance of the instruction contains a reference to a logical floating point register. A first rename phase is performed to convert the current's instance reference to the logical floating point register into a reference to an absolute register. A second rename phase is performed in parallel with the first rename phase to convert the reference to the absolute register into a reference to a physical register, based upon results obtained from performing the first rename phase with respect to a previous instance of the instruction.
摘要翻译：根据本发明的一个方面，提供一种接收指令的当前实例的方法。指令的当前实例包含对逻辑浮点寄存器的引用。执行第一重命名阶段以将当前的实例引用转换为逻辑浮点寄存器，以引用到绝对寄存器。与第一重命名阶段并行地执行第二重命名阶段，以基于相对于先前的指令实例执行第一重命名阶段获得的结果，将对绝对寄存器的引用转换为对物理寄存器的引用。

59. 发明授权

US06675376B2 System and method for fusing instructions 有权
标题翻译：用于定影指令的系统和方法
公开(公告)号：US06675376B2
公开(公告)日：2004-01-06
申请号：US09752233
申请日：2000-12-29
申请人： Ronny Ronen , Alexander Peleg , Nathaniel Hoffman
发明人： Ronny Ronen , Alexander Peleg , Nathaniel Hoffman
IPC分类号： G06F945
CPC分类号： G06F9/3001 , G06F9/30123 , G06F9/3017 , G06F9/3853 , G06F9/3893
摘要： A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed. In one embodiment, the execution unit has two arithmetic logic units (“ALUs”), each of the ALUs performs one of the two operations of the fused instruction. The result of the first ALU is input into the second ALU to produce the desired result.
摘要翻译：描述用于产生融合指令的系统和方法。在一个实施例中，作为简单指令（例如，仅执行一个操作）并且是依赖的第一指令和第二指令被融合在一起以创建融合指令。融合指令具有表示由第一指令执行的操作和由第二指令执行的操作的操作码。融合指令有三个源操作数和一个目标操作数。三个源操作数中的两个是第一个指令的两个源操作数，第三个源操作数是不是第一个指令的目标操作数的第二个指令的源操作数。融合指令的目标操作数是第二条指令的目标操作数。还公开了可以在一个时钟周期执行融合指令的执行单元。在一个实施例中，执行单元具有两个算术逻辑单元（“ALU”），每个ALU执行融合指令的两个操作之一。将第一ALU的结果输入到第二ALU中以产生期望的结果。

60. 发明授权

US06601155B2 Hot way caches: an energy saving technique for high performance caches 有权
标题翻译：热门缓存：高性能缓存的节能技术
公开(公告)号：US06601155B2
公开(公告)日：2003-07-29
申请号：US09823170
申请日：2001-03-29
申请人： Evgeni Krimer , Bishara Shomar , Ronny Ronen
发明人： Evgeni Krimer , Bishara Shomar , Ronny Ronen
IPC分类号： G06F1208
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a memory. The method includes processing a first plurality of memory cells and a second plurality of memory cells in the memory. The method determines if a memory block is a last recently accessed memory block. The method determines whether a memory block accessed is a hit or a miss. The method accesses a lower memory level if the memory block accessed is a miss. Also, processing the second plurality of memory cells for an exact block if the block accessed is a hit but not the last recently accessed memory block. And, providing the memory block for additional access if the memory block accessed is a hit and is a last recently accessed memory block.
摘要翻译：呈现包括处理器的设备。本地存储器连接到处理器。处理器包括热路缓存访问过程。提出了一种包括访问存储器的方法。该方法包括处理存储器中的第一多个存储单元和第二多个存储单元。该方法确定存储器块是否是最近最近访问的存储器块。该方法确定访问的存储器块是否是命中或未命中。如果访问的存储器块是错误的，该方法访问较低的存储器级别。此外，如果访问的块是命中而不是最近最近访问的存储器块，则处理第二多个存储器单元用于精确块。并且，如果访问的存储器块是命中并且是最后最近访问的存储器块，则提供用于附加访问的存储器块。

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