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51. 发明授权

US09824008B2 Cache memory sharing in a multi-core processor (MCP) 有权
公开(公告)号：US09824008B2
公开(公告)日：2017-11-21
申请号：US12275552
申请日：2008-11-21
申请人： Karl J. Duvalsaint , Daeik Kim , Moon J. Kim
发明人： Karl J. Duvalsaint , Daeik Kim , Moon J. Kim
IPC分类号： G06F12/08 , G06F12/0811 , G06F11/16 , G06F12/0813 , G06F11/20 , G06F12/084 , G06F12/0888
CPC分类号： G06F12/0811 , G06F11/1666 , G06F11/2035 , G06F11/2043 , G06F12/0813 , G06F12/084 , G06F12/0888 , G06F2212/1032
摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

52. 发明申请

US20160301821A9 TIME-VARYING BARCODE IN AN ACTIVE DISPLAY 审中-公开
标题翻译：活动显示器中的时变条形码
公开(公告)号：US20160301821A9
公开(公告)日：2016-10-13
申请号：US13661443
申请日：2012-10-26
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06F17/00
CPC分类号： H04N1/047 , G06K7/10722 , G06K7/1095 , G06K7/1447 , G06K19/06028 , G06K19/06075 , G06K19/06112 , H04B10/116 , H04N1/028
摘要： Embodiments of the present invention provide time-varying barcodes in an active display for information exchange. Specifically, embodiments of the present invention provide a system and method for communicating information between electronic devices via a barcode image sequence. In a typical embodiment, a barcode image sequence is displayed on the display screen of a first electronic device. A second electronic device reads and decodes the barcode image sequence. The second electronic device displays an acknowledgement on the display screen of the second electronic device. The acknowledgement is read by the first electronic device.
摘要翻译：本发明的实施例在用于信息交换的活动显示器中提供时变条形码。具体地，本发明的实施例提供了一种用于经由条形码图像序列在电子设备之间传送信息的系统和方法。在典型的实施例中，条形码图像序列显示在第一电子设备的显示屏上。第二电子设备读取和解码条形码图像序列。第二电子设备在第二电子设备的显示屏幕上显示确认。该确认由第一电子设备读取。

53. 发明授权

US09190371B2 Self-organizing network with chip package having multiple interconnection configurations 有权
标题翻译：具有多个互连配置的芯片封装的自组织网络
公开(公告)号：US09190371B2
公开(公告)日：2015-11-17
申请号：US12974165
申请日：2010-12-21
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： H01L23/02 , H01L23/00 , H01L25/065 , H01L23/48 , H01L23/525 , H01L23/528
CPC分类号： H01L25/0657 , G06F13/4022 , G06F13/4068 , H01L23/481 , H01L23/525 , H01L23/5283 , H01L24/06 , H01L24/14 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/50 , H01L2224/02371 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06188 , H01L2224/13025 , H01L2224/14181 , H01L2224/14183 , H01L2224/16137 , H01L2224/16146 , H01L2224/16157 , H01L2224/81191 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/05552
摘要： In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs.
摘要翻译：通常，本发明的实施例提供具有多个TSV配置的芯片封装。具体地，芯片封装通常包括后端层（例如，金属互连层）; 耦合到所述后端层的衬底; 从后端层的侧表面延伸（例如角度地）到后端层的底表面的一组（至少一个）后端侧互连; 一组可选的垂直TSV，从后端层的顶表面延伸穿过衬底; 以及位于基板组织器中的网络组织器，用于处理使用该组后端侧互连和一组垂直TSV形成的通信。可以将一组连接（例如，可控制的崩溃芯片连接（C4））定位成与任何通孔相邻，以连接到其他硬件元件，例如附加的芯片封装，总线等。其中，使用后端侧互连允许使用芯片封装的最大表面积并提供增加的可靠性。当与垂直TSV结合使用时，这些优点特别实现。

54. 发明授权

US09189723B2 Light-powered smart card for on-line transaction processing 有权
标题翻译：用于在线交易处理的轻型智能卡
公开(公告)号：US09189723B2
公开(公告)日：2015-11-17
申请号：US13947722
申请日：2013-07-22
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06K5/00 , G06K19/07 , G06K19/077
CPC分类号： G06K19/0708 , G06K5/00 , G06K19/0704 , G06K19/0707 , G06K19/0718 , G06K19/07707 , G06K19/07749
摘要： In general, embodiments of the present invention relate to a light-powered smart card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises (among other things) an energy component for providing power to the card. Upon powering up via a light source, including light from the interfacing terminal's backlight, a terminal (e.g., a point of sale terminal) will scan/read card information shared between the card and the card company (e.g., upon swiping or placing of the card), and generate a corresponding source validation code (SVC). An optional imager/image array positioned on the back of the card will scan/read the SVC, and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC).
摘要翻译：通常，本发明的实施例涉及一种光功率智能卡以及根据商业交易的用于自动信息（静态和动态）交换的相关方法。在典型的实施例中，卡（例如，信用卡，借记卡和/或智能卡）包括用于向卡提供电力的能量组件（尤其是）。通过光源（包括来自接口终端的背光的光）上电时，终端（例如，销售点终端）将扫描/读取卡和卡公司之间共享的卡信息（例如，在刷卡或放置卡），并生成相应的源验证码（SVC）。位于卡背面的可选的成像器/图像阵列将扫描/读取SVC，卡上的卡验证码（CVC）逻辑将生成基于SVC的CVC（例如，基于SVC的验证结果）。

55. 发明授权

US09165295B2 Automated card information exchange pursuant to a commercial transaction 有权
标题翻译：根据商业交易自动信用卡信息交换
公开(公告)号：US09165295B2
公开(公告)日：2015-10-20
申请号：US13103682
申请日：2011-05-09
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G05B19/00 , G06Q20/32 , G06K19/07 , G06Q20/40 , G07F7/08
CPC分类号： G06Q20/3278 , G06K19/0728 , G06Q20/40145 , G07F7/0893
摘要： In general, embodiments of the present invention relate to a card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises an energy component for providing power to the card and a back display (e.g., positioned on the back or magnetic strip side of the card) for displaying card information being used in the commercial transaction. Upon display, a terminal (e.g., a point of sale terminal) will scan/read the card information and generate a corresponding source validation code (SVC). An imager positioned on the back of the card will scan/read the SVC and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC). A biometric reader positioned on a front side of the card will take a biometric reading from a user of the card and corresponding user validation code (UVC) logic will generate a UVC based on the biometric reading. The underlying commercial transaction can then be validated (e.g., by a server associated with the terminal or by validation logic on the card itself), a validation result can be displayed on a front display (e.g., positioned on the front side of the card).
摘要翻译：一般来说，本发明的实施例涉及一种用于根据商业交易的自动化信息（静态和动态）交换的卡和相关方法。在典型的实施例中，卡（例如，信用卡，借记卡和/或智能卡）包括用于向卡提供电力的能量组件和背面显示器（例如，位于背面或磁条侧的卡），用于显示在商业交易中使用的卡信息。在显示时，终端（例如，销售点终端）将扫描/读取卡信息并生成相应的源验证码（SVC）。位于卡背面的成像器将扫描/读取SVC，并且卡上的卡验证码（CVC）逻辑将基于SVC生成CVC（例如，基于SVC的验证结果）。位于卡的前侧的生物识别读取器将从卡的用户进行生物特征读取，并且相应的用户验证码（UVC）逻辑将基于生物特征读数生成UVC。然后可以验证基础商业交易（例如，通过与终端相关联的服务器或卡上的验证逻辑），可以在前显示器（例如，位于卡的前侧）上显示验证结果，。

56. 发明授权

US09122617B2 Pseudo cache memory in a multi-core processor (MCP) 有权
标题翻译：多核处理器（MCP）中的伪缓存存储器
公开(公告)号：US09122617B2
公开(公告)日：2015-09-01
申请号：US12276069
申请日：2008-11-21
申请人： Karl J. Duvalsaint , Daeik Kim , Moon J. Kim
发明人： Karl J. Duvalsaint , Daeik Kim , Moon J. Kim
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0828 , G06F12/0833 , G06F2212/621
摘要： Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches.
摘要翻译：具体地说，在本发明中，高速缓冲存储器单元可以被指定为公共层级内的另一高速缓冲存储器单元的伪高速缓冲存储器单元。例如，在层次结构的高速缓存级L2上的高速缓存存储器单元“X”处的高速缓存未命中的情况下，将请求发送到高速缓存级L3（外部）上的高速缓冲存储器单元以及一个或多个其他高速缓冲存储器单元在缓存级L2上。 L2级缓存单元返回搜索结果作为命中或未命中。它们通常不会搜索L3，也不会用L3结果写回（即使结果是错过）。在这个程度上，如果所有的L2都错过，只有请求的直接起始点才会用L3结果写回来。这样，其他L2级高速缓冲存储器单元用作原始高速缓存存储器单元作为伪高速缓存。

57. 发明申请

US20150046660A1 ACTIVE MEMORY PROCESSOR SYSTEM 有权
标题翻译：主动存储处理器系统
公开(公告)号：US20150046660A1
公开(公告)日：2015-02-12
申请号：US14523153
申请日：2014-10-24
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06F12/08
CPC分类号： G06F12/0884 , G06F12/0806 , G06F12/0831 , G06F12/0833 , G06F12/0835 , G06F12/0877 , G06F2212/6012 , G06F2212/62 , G06F2212/621
摘要： In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.
摘要翻译：通常，本发明涉及数据高速缓存处理。具体而言，本发明涉及一种提供可重新配置的动态高速缓存的系统，该系统可以根据来自不同的外部通用处理器核心的应用的需求以及虚拟混合核心系统的功能来改变高速缓冲存储器的操作策略。该系统包括接收数据请求，基于数据请求选择操作模式和预定义的选择算法，以及基于所选择的操作模式处理数据请求。

58. 发明授权

US08935143B2 Semiconductor sensor reliability 有权
标题翻译：半导体传感器的可靠性
公开(公告)号：US08935143B2
公开(公告)日：2015-01-13
申请号：US12968632
申请日：2010-12-15
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06F17/50 , G06G7/62 , H01L23/58 , H01L29/10 , G01R31/28
CPC分类号： G06F17/5072 , G01R31/2856 , G06F2217/14 , G06F2217/76
摘要： Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.
摘要翻译：本发明的实施例提供一种半导体传感器可靠性系统和方法。具体地，本发明提供了可靠性传感器（以下称为传感器）在半导体系统的各个功能块内以及关键位置的原位定位。传感器的数量和位置被优化，以对已知的工艺变化具有最大的灵敏度。通常，传感器对其所在的位置（例如，功能块）的行为（例如，老化处理）进行建模，并且包括作为网络连接的多个级和自数字化器。每个传感器具有用于选择其模式的模式选择输入和用于使传感器对行为进行建模的操作触发输入。模型选择输入和操作触发使得传感器具有其中多个传感器经历衰老过程的操作模式以及输出多个传感器的年龄的测量模式。

59. 发明授权

US08775840B2 Virtualization in a multi-core processor (MCP) 有权
标题翻译：多核处理器（MCP）中的虚拟化
公开(公告)号：US08775840B2
公开(公告)日：2014-07-08
申请号：US13563160
申请日：2012-07-31
申请人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
发明人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
IPC分类号： G06F1/26 , G06F1/00 , G06F7/38
CPC分类号： G06F9/5077 , Y02D10/22 , Y02D10/36
摘要： This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.
摘要翻译：本发明描述了用于MPE的设备，计算机体系结构，方法，操作系统，编译器和应用程序产品以及对称MCP中的虚拟化。本公开应用于具有一组（例如，一个或多个）控制元件（例如，MPE）和一组子处理元件（例如，SPE）的通用微处理器架构。在这种安排下，MPEs和SPE的组织方式是以较小数量的MPE来控制一组SPE的行为。该设备使得MPE内的虚拟化控制线程可以分配给不同的SPE组，以便控制它们。该装置还包括耦合到与核耦合的电源的MCP以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。

60. 发明授权

US08732716B2 Virtualization across physical partitions of a multi-core processor (MCP) 有权
标题翻译：跨多核处理器（MCP）物理分区的虚拟化
公开(公告)号：US08732716B2
公开(公告)日：2014-05-20
申请号：US12241429
申请日：2008-09-30
申请人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
发明人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
IPC分类号： G06F9/50
CPC分类号： G06F9/5077 , G06F9/45533 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.
摘要翻译：除其他之外，本公开应用于具有一组（例如，一个或多个）控制/主处理元件（例如MPE）和一组子处理元件（例如SPE）的通用微处理器架构。在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。该装置包括耦合到与核耦合的电源的MCP，以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。根据这些特征，虚拟化控制线程可以遍历MCP的物理边界以控制不同物理分区（例如，不同于其中的物理分区）的SPE（例如，具有一个或多个SPE的逻辑分区）虚拟化控制线程发起。

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