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51. 发明授权

US07531367B2 Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权
标题翻译：利用侧壁间隔物特征在集成电路中形成磁隧道结
公开(公告)号：US07531367B2
公开(公告)日：2009-05-12
申请号：US11333997
申请日：2006-01-18
申请人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
发明人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译：描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

52. 发明申请

US20090091037A1 Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits 有权
标题翻译：在集成电路中制造与柱结构的接触的方法
公开(公告)号：US20090091037A1
公开(公告)日：2009-04-09
申请号：US11866455
申请日：2007-10-03
申请人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
发明人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L43/12
摘要： A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.
摘要翻译：在集成电路中形成由垂直接触件接触的柱结构。硬掩模被形成并用于对柱结构的至少一部分进行图案化。硬掩模包含碳。随后，去除硬掩模。然后将导电材料沉积在先前由硬掩模占据的区域中以形成垂直接触。硬掩模可以例如包括类金刚石碳。柱结构可以具有小于约100纳米的宽度或直径。

53. 发明申请

US20080164617A1 Method of Forming Vertical Contacts in Integrated Circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US20080164617A1
公开(公告)日：2008-07-10
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

54. 发明授权

US07248615B2 Electrically-activated photonic crystal microcavity laser 失效
标题翻译：电激活光子晶体微腔激光器
公开(公告)号：US07248615B2
公开(公告)日：2007-07-24
申请号：US10721841
申请日：2003-11-25
申请人： Solomon Assefa , Leslie A. Kolodziekski , Gale S. Petrich
发明人： Solomon Assefa , Leslie A. Kolodziekski , Gale S. Petrich
IPC分类号： H01S3/08
CPC分类号： H01S5/10 , B82Y20/00 , H01S5/1042 , H01S5/105 , H01S5/3412
摘要： A microcavity structure includes a first waveguide that includes a first photonic crystal microcavity. A second waveguide includes a second photonic crystal microcavity. A microcavity active region is created by overlapping the first and second microcavities.
摘要翻译：微腔结构包括包括第一光子晶体微腔的第一波导。第二波导包括第二光子晶体微腔。通过重叠第一和第二微腔来产生微腔活性区域。

55. 发明授权

US09134479B2 Polarization diverse demultiplexing 有权
标题翻译：极化多样化解复用
公开(公告)号：US09134479B2
公开(公告)日：2015-09-15
申请号：US13603811
申请日：2012-09-05
申请人： Solomon Assefa , Douglas M. Gill , William M. Green
发明人： Solomon Assefa , Douglas M. Gill , William M. Green
IPC分类号： H04B10/00 , G02B6/12 , G02B6/27 , G02B6/293
CPC分类号： G02B6/12023 , G02B6/2793 , G02B6/293
摘要： An optical demultiplexing device includes a first portion operative to receive an input optical signal having a first polarization, a second polarization and multiple channels, and split the input optical signal into a first optical signal having the first polarization and a second optical signal having the first polarization, and an optical demultiplexing portion communicatively connected to the polarization splitter portion, the optical demultiplexing portion operative to receive a combination of the first optical signal and the second optical signal, and output each channel of the first optical signal and the second optical signal to a photodetector device corresponding to each channel.
摘要翻译：光解复用装置包括第一部分，其操作以接收具有第一偏振光，第二偏振光和多通道的输入光信号，并将输入光信号分离为具有第一偏振的第一光信号和具有第一偏振的第二光信号偏振光，以及通信地连接到偏振分离器部分的光解复用部分，光解复用部分用于接收第一光信号和第二光信号的组合，并将第一光信号和第二光信号的每个通道输出到对应于每个通道的光电检测器装置。

56. 发明申请

US20140029950A1 OPTICAL DE-MULTIPLEXING DEVICE 审中-公开
标题翻译：光学多路复用器件
公开(公告)号：US20140029950A1
公开(公告)日：2014-01-30
申请号：US13562817
申请日：2012-07-31
申请人： Solomon Assefa , Douglas M. Gill , Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow
发明人： Solomon Assefa , Douglas M. Gill , Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow
IPC分类号： H04J14/02
CPC分类号： G02B6/12019 , H04B10/676 , H04B10/691 , H04B10/697 , H04B10/6972 , H04B17/20 , H04J14/02
摘要： A method for controlling an output of an electro-optical de-multiplexing device, the method including identifying which photodetector of a first array of photodetectors is converting a first channel of an optical signal into a first electrical channel signal, and affecting a communicative connection between the identified photodetector of the first array of photodetectors that is converting the first channel of the optical signal into the first electrical channel signal and a first output node associated with the first electrical channel signal.
摘要翻译：一种用于控制电光解复用装置的输出的方法，所述方法包括识别第一阵列的光电检测器的哪个光电检测器将光信号的第一通道转换为第一电通道信号，并且影响第一阵列的光电检测器的所识别的光电检测器将光信号的第一通道转换成第一电通道信号，以及与第一电通道信号相关联的第一输出节点。

57. 发明申请

US20130330037A1 EXCITING A SELECTED MODE IN AN OPTICAL WAVEGUIDE 审中-公开
公开(公告)号：US20130330037A1
公开(公告)日：2013-12-12
申请号：US13527207
申请日：2012-06-19
申请人： Solomon Assefa , Huapu Pan , Yurii Vlasov
发明人： Solomon Assefa , Huapu Pan , Yurii Vlasov
IPC分类号： G02B6/26
CPC分类号： G02B6/12002 , G02B6/14 , G02B2006/12123 , G02B2006/1215 , G02B2006/12195 , H01L31/02327
摘要： A method of exciting a selected light propagation mode in a device is disclosed. At least two light beams are propagated proximate a waveguide of the device substantially parallel to a selected surface of the waveguide. Light is transferred from the at least two beams of light into the waveguide through the selected surface to excite the selected light propagation mode in the waveguide.

58. 发明授权

US08363686B2 Temperature control device for optoelectronic devices 有权
标题翻译：光电器件温度控制装置
公开(公告)号：US08363686B2
公开(公告)日：2013-01-29
申请号：US13363995
申请日：2012-02-01
申请人： Solomon Assefa , William M. Green , Younghee Kim , Joris Van Campenhout , Yurii Vlasov
发明人： Solomon Assefa , William M. Green , Younghee Kim , Joris Van Campenhout , Yurii Vlasov
IPC分类号： H01S5/00
CPC分类号： H01L35/34 , G02B6/12004 , G02B6/1347 , G02B2006/12069 , G02F1/0147 , G02F1/025
摘要： Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.
摘要翻译：电流可以通过n掺杂半导体区域，凹陷金属半导体合金部分和p掺杂半导体区域，使得掺杂半导体区域中的多数电荷载流子的扩散通过Peltier- 塞贝克效应。此外，温度控制装置可以被配置为包括位于光电子器件附近的金属半导体合金区域，具有p型掺杂的第一半导体区域和具有n型掺杂的第二半导体区域。因此可以控制光电子器件的温度以稳定光电器件的性能。

59. 发明申请

US20120115251A1 PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE 失效
标题翻译：用于选择性地绘制磁性膜结构的方法
公开(公告)号：US20120115251A1
公开(公告)日：2012-05-10
申请号：US13350174
申请日：2012-01-13
申请人： David W. Abraham , Solomon Assefa , Eugene J. O'Sullivan
发明人： David W. Abraham , Solomon Assefa , Eugene J. O'Sullivan
IPC分类号： H01L21/465
CPC分类号： H01L43/12
摘要： Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.
摘要翻译：用于选择性地图案化磁性膜结构的方法通常包括通过湿法选择性地蚀刻设置在隧道势垒层上的自由层的暴露部分，其包括将自由层暴露于包含至少一种酸和有机磷酸抑制剂或盐的蚀刻剂溶液在隧道势垒层上停止。

60. 发明授权

US08008095B2 Methods for fabricating contacts to pillar structures in integrated circuits 有权
标题翻译：在集成电路中制造与柱结构接触的方法
公开(公告)号：US08008095B2
公开(公告)日：2011-08-30
申请号：US11866455
申请日：2007-10-03
申请人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
发明人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.
摘要翻译：在集成电路中形成由垂直接触件接触的柱结构。硬掩模被形成并用于对柱结构的至少一部分进行图案化。硬掩模包含碳。随后，去除硬掩模。然后将导电材料沉积在先前由硬掩模占据的区域中以形成垂直接触。硬掩模可以例如包括类金刚石碳。柱结构可以具有小于约100纳米的宽度或直径。

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