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51. 发明申请

US20130043549A1 Hole First Hardmask Definition 有权
标题翻译：孔第一硬掩模定义
公开(公告)号：US20130043549A1
公开(公告)日：2013-02-21
申请号：US13618908
申请日：2012-09-14
申请人： Wei-Hang Huang , Shih-Chang Liu , Chern-Yow Hsu , Fu-Ting Sung , Chia-Shiung Tsai
发明人： Wei-Hang Huang , Shih-Chang Liu , Chern-Yow Hsu , Fu-Ting Sung , Chia-Shiung Tsai
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , G11C11/16
摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.
摘要翻译：提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。顶部电极可以具有倾斜的侧壁。可以通过沉积相应的MTJ层来形成MTJ堆叠。可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。开口填充有导电材料以形成顶部电极。然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

52. 发明申请

US20130034929A1 Method for Forming CMOS Image Sensors 有权
标题翻译： CMOS图像传感器的形成方法
公开(公告)号：US20130034929A1
公开(公告)日：2013-02-07
申请号：US13196560
申请日：2011-08-02
申请人： Ching-Chung Su , Shih-Chang Liu , Shih Pei Chou , Chia-Shiung Tsai , Chun-Tsung Kuo , Wen-I Hsu , Yi-Shin Chu
发明人： Ching-Chung Su , Shih-Chang Liu , Shih Pei Chou , Chia-Shiung Tsai , Chun-Tsung Kuo , Wen-I Hsu , Yi-Shin Chu
IPC分类号： H01L31/18
CPC分类号： H01L27/1463
摘要： A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.
摘要翻译：一种方法包括在衬底上形成阻挡层，并蚀刻阻挡层以在阻挡层中形成沟槽。形成介电层，其中电介质层包括阻挡层上的第一部分和沟槽中的第二部分。在形成介电层的步骤之后，进行注入以将杂质注入衬底以形成深阱区。在植入之后，去除介电层和阻挡层。

53. 发明授权

US08313959B1 Hole first hardmask definition 有权
标题翻译：孔第一硬掩模定义
公开(公告)号：US08313959B1
公开(公告)日：2012-11-20
申请号：US13211909
申请日：2011-08-17
申请人： Wei-Hang Huang , Shih-Chang Liu , Chern-Yow Hsu , Fu-Ting Sung , Chia-Shiung Tsai
发明人： Wei-Hang Huang , Shih-Chang Liu , Chern-Yow Hsu , Fu-Ting Sung , Chia-Shiung Tsai
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , G11C11/16
摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.
摘要翻译：提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。顶部电极可以具有倾斜的侧壁。可以通过沉积相应的MTJ层来形成MTJ堆叠。可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。开口填充有导电材料以形成顶部电极。然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

54. 发明申请

US20050082601A1 Split gate field effect transistor with a self-aligned control gate 审中-公开
标题翻译：具有自对准控制栅极的分流栅场效应晶体管
公开(公告)号：US20050082601A1
公开(公告)日：2005-04-21
申请号：US10689462
申请日：2003-10-20
申请人： Wen-Ting Chu , Shih-Chang Liu
发明人： Wen-Ting Chu , Shih-Chang Liu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method of forming a split gate field effect transistor and a structure of the split gate field effect transistor are provided. The method of forming the split gate effect transistor firstly provides a substrate having a pair of floating gates, a first conductive material layer between the pair of floating gates, and a first dielectric layer above the first conductive material layer. Then a control gate is formed. The control gate has a second dielectric layer above the control gate, wherein the control gate is self-aligned to the pair of floating gates by using the first and second dielectric layers as an etching hard mask. Finally, a pair of source/drain regions are formed into said substrate and beside said pair of floating gates and said control gate.
摘要翻译：提供了形成分裂栅极场效应晶体管的方法和分离栅极场效应晶体管的结构。形成分裂栅效应晶体管的方法首先提供了具有一对浮置栅极的衬底，在一对浮置栅极之间的第一导电材料层和位于第一导电材料层上方的第一电介质层。然后形成控制门。控制栅极具有在控制栅极上方的第二介电层，其中通过使用第一和第二介电层作为蚀刻硬掩模，控制栅极与一对浮置栅极自对准。最后，一对源极/漏极区域形成在所述衬底中以及所述一对浮置栅极和所述控制栅极旁边。

55. 发明申请

US20120261781A1 SIDEWALL FOR BACKSIDE ILLUMINATED IMAGE SENSOR METAL GRID AND METHOD OF MANUFACTURING SAME 有权
标题翻译：背面照明图像传感器金属网及其制造方法
公开(公告)号：US20120261781A1
公开(公告)日：2012-10-18
申请号：US13087192
申请日：2011-04-14
申请人： Hung-Wen Hsu , Shih-Chang Liu , Yeur-Luen Tu
发明人： Hung-Wen Hsu , Shih-Chang Liu , Yeur-Luen Tu
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14685 , H01L27/14623 , H01L27/14627 , H01L27/1464
摘要： The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature.
摘要翻译：本公开提供了一种图像传感器装置和用于制造图像传感器装置的方法。示例性的图像传感器装置包括具有前表面和后表面的基板; 设置在所述基板的前表面处的多个传感器元件，所述多个传感器元件中的每一个可操作以感测朝向所述基板的后表面投射的辐射; 辐射屏蔽特征设置在所述基板的所述背表面上并且水平地设置在所述多个传感器元件中的每一个之间; 设置在基板的背面和辐射屏蔽特征之间的电介质特征; 以及沿着电介质特征的侧壁设置的金属层。

56. 发明申请

US20050112828A1 METHOD TO FORM FLASH MEMORY WITH VERY NARROW POLYSILICON SPACING 有权
标题翻译：用非常窄的多晶硅间隔形成闪存的方法
公开(公告)号：US20050112828A1
公开(公告)日：2005-05-26
申请号：US10719722
申请日：2003-11-21
申请人： Wen-Ting Chu , Shih-Chang Liu
发明人： Wen-Ting Chu , Shih-Chang Liu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/76 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.
摘要翻译：实现了在制造集成电路器件中形成晶体管栅极的新方法。该方法包括提供基底。导体层形成在衬底之上，其间具有介电层。形成覆盖在导体层上的掩模层。形成覆盖掩模层的抗蚀剂层。图案化抗蚀剂层，从而选择性地暴露掩模层。抗蚀剂层在抗蚀剂层的边缘之间呈现第一间隔。暴露的掩模层被蚀刻通过，从而选择性地暴露导体层。掩模层的蚀刻边缘是锥形的，使得掩模层在导体层的顶表面处的掩模层边缘之间呈现第二间隔。第二个间距小于第一个间距。蚀刻暴露的导体层从而完成晶体管栅极。

57. 发明授权

US5933343A Multi-deck power converter module 失效
标题翻译：多层电源转换器模块
公开(公告)号：US5933343A
公开(公告)日：1999-08-03
申请号：US158221
申请日：1998-09-22
申请人： Qun Lu , Paul E. Grandmont , Shih-Chang Liu
发明人： Qun Lu , Paul E. Grandmont , Shih-Chang Liu
IPC分类号： H02M3/00 , H05K1/14 , H02M1/00
CPC分类号： H05K1/144 , H02M3/00 , H02M7/003
摘要： A multi-deck power converter module assembly for connection with a substrate (e.g., a host board) having connection regions disposed on its surface includes a second circuit board positioned over a first circuit board, the second circuit board having apertures extending from an upper surface to a lower surface of the second circuit board. At least two rail members are positioned over the second circuit board, each rail member having a first and a second plurality of holes. A pair of spacers are disposed between the first and second circuit boards, each spacer extending through one of the apertures of the second circuit board and received within one of the first plurality of holes of one of the rail members. Terminal pins are attached to the first circuit board, at least one terminal pin extending through the second circuit board and a corresponding one of the second plurality of holes for connection to one of the connection regions on the substrate. Each of the second plurality of holes is sized to allow the rail members to be slidably positioned over the terminal pins during assembly of the power converter module.
摘要翻译：用于与具有设置在其表面上的连接区域的基板（例如，主板）连接的多层电力转换器模块组件包括位于第一电路板上的第二电路板，第二电路板具有从上表面到第二电路板的下表面。至少两个轨道构件定位在第二电路板上方，每个轨道构件具有第一和第二多个孔。一对间隔件设置在第一和第二电路板之间，每个间隔件延伸穿过第二电路板的一个孔并被接纳在一个轨道构件的第一多个孔中的一个孔内。端子销附接到第一电路板，延伸穿过第二电路板的至少一个端子引脚和用于连接到基板上的一个连接区域的第二多个孔中的相应一个。第二多个孔中的每一个的尺寸被设计成允许轨道构件在组装功率转换器模块期间可滑动地定位在端子销上方。

58. 发明授权

US08610229B2 Sidewall for backside illuminated image sensor metal grid and method of manufacturing same 有权
标题翻译：背面照明图像传感器金属网格的侧壁及其制造方法
公开(公告)号：US08610229B2
公开(公告)日：2013-12-17
申请号：US13087192
申请日：2011-04-14
申请人： Hung-Wen Hsu , Shih-Chang Liu , Yeur-Luen Tu
发明人： Hung-Wen Hsu , Shih-Chang Liu , Yeur-Luen Tu
IPC分类号： H01L27/146
CPC分类号： H01L27/14685 , H01L27/14623 , H01L27/14627 , H01L27/1464
摘要： The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature.
摘要翻译：本公开提供了一种图像传感器装置和用于制造图像传感器装置的方法。示例性的图像传感器装置包括具有前表面和后表面的基板; 设置在所述基板的前表面处的多个传感器元件，所述多个传感器元件中的每一个可操作以感测朝向所述基板的后表面投射的辐射; 辐射屏蔽特征设置在所述基板的所述背表面上并且水平地设置在所述多个传感器元件中的每一个之间; 设置在基板的背面和辐射屏蔽特征之间的电介质特征; 以及沿着电介质特征的侧壁设置的金属层。

59. 发明授权

US06924199B2 Method to form flash memory with very narrow polysilicon spacing 有权
标题翻译：形成具有非常窄的多晶硅间隔的闪存的方法
公开(公告)号：US06924199B2
公开(公告)日：2005-08-02
申请号：US10719722
申请日：2003-11-21
申请人： Wen-Ting Chu , Shih-Chang Liu
发明人： Wen-Ting Chu , Shih-Chang Liu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/76 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.
摘要翻译：实现了在集成电路器件的制造中形成晶体管栅极的新方法。该方法包括提供基底。导体层形成在衬底之上，其间具有介电层。形成覆盖在导体层上的掩模层。形成覆盖掩模层的抗蚀剂层。图案化抗蚀剂层，从而选择性地暴露掩模层。抗蚀剂层在抗蚀剂层的边缘之间呈现第一间隔。暴露的掩模层被蚀刻通过，从而选择性地暴露导体层。掩模层的蚀刻边缘是锥形的，使得掩模层在导体层的顶表面处的掩模层边缘之间呈现第二间隔。第二个间距小于第一个间距。蚀刻暴露的导体层从而完成晶体管栅极。

60. 发明授权

US5812387A Multi-deck power converter module 失效
公开(公告)号：US5812387A
公开(公告)日：1998-09-22
申请号：US803980
申请日：1997-02-21
申请人： Qun Lu , Paul E. Grandmont , Shih-Chang Liu
发明人： Qun Lu , Paul E. Grandmont , Shih-Chang Liu
IPC分类号： H02M3/00 , H05K1/14 , H02M1/00
CPC分类号： H05K1/144 , H02M3/00 , H02M7/003
摘要： A multi-deck power converter module assembly for connection with a substrate (e.g., a host board) having connection regions disposed on its surface includes a second circuit board positioned over a first circuit board, the second circuit board having apertures extending from an upper surface to a lower surface of the second circuit board. At least two rail members are positioned over the second circuit board, each rail member having a first and a second plurality of holes. A pair of spacers are disposed between the first and second circuit boards, each spacer extending through one of the apertures of the second circuit board and received within one of the first plurality of holes of one of the rail members. Terminal pins are attached to the first circuit board, at least one terminal pin extending through the second circuit board and a corresponding one of the second plurality of holes for connection to one of the connection regions on the substrate. Each of the second plurality of holes is sized to allow the rail members to be slidably positioned over the terminal pins during assembly of the power converter module.

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