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    • 52. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08719615B2
    • 2014-05-06
    • US13064316
    • 2011-03-17
    • Yohei HasegawaYutaka YamadaTakashi YoshikawaShigehiro Asano
    • Yohei HasegawaYutaka YamadaTakashi YoshikawaShigehiro Asano
    • G06F1/12
    • G06F1/12G06F9/3887G06F9/3893
    • A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.
    • 半导体器件与某个时钟信号同步地进行操作。 该半导体装置包括用于输出操作控制信息的控制单元,用于存储数据的存储单元,用于根据第一操作控制信息对第一数据执行操作的第一操作单元和用于对第二数据执行操作的第二操作单元 根据第二操作控制信息。 第一操作单元包括多个操作电路。 构成整个运算电路的逻辑门的数量为m。 第二操作单元包括其中逻辑门数为n(n> m)的至少一个操作电路。 操作单元的总延迟或操作单元的总延迟中的每一个被设置为等于或小于时钟信号的周期的值。
    • 56. 发明申请
    • TROUBLE ANALYSIS APPARATUS
    • 故障分析设备
    • US20110145647A1
    • 2011-06-16
    • US13057365
    • 2009-08-04
    • Youichi HidakaTakashi YoshikawaJunichi Higuchi
    • Youichi HidakaTakashi YoshikawaJunichi Higuchi
    • G06F11/07
    • G06F11/079G06F11/0706
    • A trouble analysis apparatus is provided which includes: a system topology storing portion; an error detection information receiving portion which collects error detection information; and a trouble source determination portion which, based on both the error detection information collected by the error detection information receiving portion and system topology information stored in the system topology information storing portion, determines a trouble source functional element that is presumed as a functional element which is a source of a system trouble. Links included in the system topology information have information indicating spreading directions of error operations between the functional elements when trouble occurs. When the trouble source detection portion receives the error detection information with regard to multiple error functional elements, the trouble source determination portion sequentially selects one of the multiple error functional elements. The trouble source detection portion determines whether or not directions from the selected error functional element to other error functional elements conform to the spreading directions included in the system topology information. The trouble source determination portion determines the selected error functional element as the trouble source functional element when the spreading directions are conformable.
    • 提供一种故障分析装置,包括:系统拓扑存储部; 错误检测信息接收部分,其收集错误检测信息; 以及故障源确定部,其基于由所述错误检测信息接收部收集的所述错误检测信息和存储在所述系统拓扑信息存储部中的系统拓扑信息,确定被认为是功能元素的故障源功能元件, 是系统麻烦的根源。 包括在系统拓扑信息中的链接具有指示当故障发生时功能元件之间的错误操作的扩展方向的信息。 当故障源检测部分接收关于多个错误功能元件的错误检测信息时,故障源确定部分依次选择多个误差功能元件中的一个。 故障源检测部分确定从所选择的误差功能元件到其他误差功能元件的方向是否符合包括在系统拓扑信息中的扩展方向。 当扩散方向一致时,故障源确定部分将所选择的误差功能元件确定为故障源功能元件。
    • 59. 发明授权
    • Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten
    • 沟通处理通信相邻的阶段和控制,以防止地址信息被覆盖
    • US07818546B2
    • 2010-10-19
    • US11517327
    • 2006-09-08
    • Shigehiro AsanoTakashi Yoshikawa
    • Shigehiro AsanoTakashi Yoshikawa
    • G06F9/00G06F7/38G06F9/44G06F13/00
    • G06F13/368
    • A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.
    • 用于在总线主机和总线从站之间传送信息的总线装置包括:能够通过流水线处理从总线主机向总线从机传输信息的多个流水线寄存器; 以及管理每个流水线寄存器的多个管理装置。 此外,管理装置包括:保持状态保持单元,其将保持状态保持为指示与管理装置对应的当前级的流水线寄存器是否保存信息的信息; 相邻级的保持状态指定单元,其指定向当前级的流水线寄存器发送信息的前一级的流水线寄存器的保持状态,以及发送来自当前级的流水线寄存器的信息的后级的流水线寄存器的保持状态; 以及传送控制单元,其确定由相应流水线寄存器保存的信息是否被传送。