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51. 发明申请

US20110019474A1 FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS 有权
标题翻译：具有冗余色谱柱的闪存存储器件
公开(公告)号：US20110019474A1
公开(公告)日：2011-01-27
申请号：US12898070
申请日：2010-10-05
申请人： Jin-Man Han , Aaron Yip
发明人： Jin-Man Han , Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C29/846 , G11C29/82 , G11C2216/30
摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
摘要翻译：公开了装置和方法，例如涉及闪存装置的装置和方法。一种这样的装置包括包括多个列的存储块。每个列包括位线和位线上的多个存储单元。多个列包括多组常规列和多组冗余列。该装置还包括多个数据锁存器。每个数据锁存器被配置为存储从相应的一组常规列读取的数据。该装置还包括多个冗余数据锁存器。每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。

52. 发明申请

US20100061155A1 MEMORY ARRAY SEGMENTATION AND METHODS 有权
标题翻译：记忆阵列分段和方法
公开(公告)号：US20100061155A1
公开(公告)日：2010-03-11
申请号：US12614750
申请日：2009-11-09
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115
摘要： An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell.
摘要翻译：一种方法的实施例包括将第一电压施加到通常耦合到分别形成在第一导电类型的多个第一阱区域的第一阱区域上的存储器单元行的部分的选定字线，所述第一阱区域形成在第一阱区域的第二阱区域中，第二导电类型，耦合到所选字线并形成在第一阱区之一上的至少一个目标存储单元，第一阱区彼此电隔离; 对未选择的字线施加第二电压，每个未选择的字线共同耦合到一行存储器单元的未被编程并分别形成在第一阱区上的部分; 以及向不包括所述至少一个目标存储单元的所述第一阱区施加第三电压。

53. 发明申请

US20090216948A1 METHOD FOR SUBSTANTIALLY UNINTERRUPTED CACHE READOUT 有权
标题翻译：用于实质性非中断高速缓存读取的方法
公开(公告)号：US20090216948A1
公开(公告)日：2009-08-27
申请号：US12437201
申请日：2009-05-07
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811
摘要： A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.
摘要翻译：一种能够顺利地输出多页缓存数据同时减轻通常由取样和传送操作引起的任何中断的存储器件。存储器件从第一页输出缓存的数据，而来自第二页的数据被提取到读出放大器电路中。当第一页的输出到达预定的传送点时，来自第二页的获取的数据的一部分在被缓存的第一页的其余部分被输出的同时被传送到高速缓存。在第二页的第一部分的输出以很少或没有中断的情况下开始输出来自第一页的所有数据之后，第二页的其余部分被传送到高速缓存。

54. 发明授权

US07532524B2 Bitline exclusion in verification operation 有权
标题翻译：验证操作中的位线排除
公开(公告)号：US07532524B2
公开(公告)日：2009-05-12
申请号：US11842531
申请日：2007-08-21
申请人： Hendrik Hartono , Aaron Yip , Benjamin Louie
发明人： Hendrik Hartono , Aaron Yip , Benjamin Louie
IPC分类号： G11C7/00
CPC分类号： G11C16/3454 , G11C29/83 , G11C29/832
摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
摘要翻译：用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作失败了

55. 发明授权

US07505323B2 Programming memory devices 失效
标题翻译：编程存储器件
公开(公告)号：US07505323B2
公开(公告)日：2009-03-17
申请号：US12025815
申请日：2008-02-05
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

56. 发明申请

US20090043975A1 MEMORY DEVICE TRIMS 有权
标题翻译：存储设备TRIMS
公开(公告)号：US20090043975A1
公开(公告)日：2009-02-12
申请号：US12246606
申请日：2008-10-07
申请人： Benjamin Louie , Aaron Yip , Jin-Man Han
发明人： Benjamin Louie , Aaron Yip , Jin-Man Han
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/028
摘要： Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.
摘要翻译：提供了方法和装置。存储器件具有存储器阵列，适用于存储存储器阵列共用的基本控制参数值的基本修剪电路以及与存储器阵列的一部分相对应的参考调整电路。参考调整电路适于存储一个或多个参考控制参数值，用于分别校正基本调整电路的基本控制参数值中的一个或多个，以供应用于存储器阵列的该部分。存储器件可以包括对应于参考调整电路的指数电路。索引电路适于存储一个或多个索引参数值，用于分别选择基本修整电路的一个或多个基本控制参数值，以通过参考调整电路的一个或多个参考控制参数值进行校正。

57. 发明授权

US07447847B2 Memory device trims 有权
标题翻译：存储设备修剪
公开(公告)号：US07447847B2
公开(公告)日：2008-11-04
申请号：US10894242
申请日：2004-07-19
申请人： Benjamin Louie , Aaron Yip , Jin-Man Han
发明人： Benjamin Louie , Aaron Yip , Jin-Man Han
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/028
摘要： Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.
摘要翻译：提供了方法和装置。存储器件具有存储器阵列，适用于存储存储器阵列共用的基本控制参数值的基本修剪电路以及与存储器阵列的一部分相对应的参考调整电路。参考调整电路适于存储一个或多个参考控制参数值，用于分别校正基本调整电路的基本控制参数值中的一个或多个，以供应用于存储器阵列的该部分。存储器件可以包括对应于参考调整电路的指数电路。索引电路适于存储一个或多个索引参数值，用于分别选择基本修整电路的一个或多个基本控制参数值，以通过参考调整电路的一个或多个参考控制参数值进行校正。

58. 发明申请

US20080130373A1 PROGRAMMING MEMORY DEVICES 失效
标题翻译：编程存储器件
公开(公告)号：US20080130373A1
公开(公告)日：2008-06-05
申请号：US12025815
申请日：2008-02-05
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

59. 发明授权

US07379365B2 Method and apparatus for charging large capacitances 有权
公开(公告)号：US07379365B2
公开(公告)日：2008-05-27
申请号：US11492765
申请日：2006-07-26
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C7/02
CPC分类号： G11C5/14 , G11C16/30
摘要： A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer routes one of an external voltage or an operating voltage derived from said external voltage to charge the capacitance depending on the output of the comparator.

60. 发明授权

US07345918B2 Selective threshold voltage verification and compaction 有权
标题翻译：选择性阈值电压验证和压实
公开(公告)号：US07345918B2
公开(公告)日：2008-03-18
申请号：US11216742
申请日：2005-08-31
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.
摘要翻译：用于提供选择性压实验证和/或选择性压缩的非易失性存储器件，以利于利用NAND架构在存储器件中紧固阈值电压分布。通过在NAND串的不到所有字线上提供压缩验证和/或压缩，可以通过在NAND串的所有字线上同时执行的现有方法来实现分配的增加的紧缩。

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