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51. 发明授权

US06441422B1 Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well 失效
标题翻译：具有接触P阱的超可扩展混合DRAM单元的结构和方法
公开(公告)号：US06441422B1
公开(公告)日：2002-08-27
申请号：US09706482
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
摘要翻译：提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。

52. 发明授权

US06440793B1 Vertical MOSFET 失效
公开(公告)号：US06440793B1
公开(公告)日：2002-08-27
申请号：US09757514
申请日：2001-01-10
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L218242
CPC分类号： H01L27/10841 , H01L21/2255 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

53. 发明授权

US06429068B1 Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect 失效
标题翻译：用硅化硅线和多晶硅互连制造嵌入式垂直DRAM阵列的结构和方法
公开(公告)号：US06429068B1
公开(公告)日：2002-08-06
申请号：US09897868
申请日：2001-07-02
申请人： Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Larry Nesbit , Carl Radens
发明人： Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Larry Nesbit , Carl Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。该工艺消除了对M0金属化层的需要。

54. 发明授权

US06426247B1 Low bitline capacitance structure and method of making same 失效
标题翻译：低位线电容结构及其制作方法
公开(公告)号：US06426247B1
公开(公告)日：2002-07-30
申请号：US09764824
申请日：2001-01-17
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21338
CPC分类号： H01L27/10888 , H01L23/485 , H01L27/10861 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.
摘要翻译：一种用于形成具有低位线电容的存储器件的方法，包括：在硅衬底上提供栅极导体堆叠结构，所述栅堆叠结构具有栅极氧化层，多晶硅层，硅化物层和顶部电介质氮化物层; 氧化所述栅极氧化层的侧壁; 在所述栅极导体堆叠的侧壁上形成侧壁间隔物，所述侧壁间隔物包括厚度范围为约50至约250埃的薄氮化物层; 用具有约25至约150埃的厚度的薄氮化物衬垫覆盖栅极结构; 在栅极结构上沉积绝缘氧化物层; 将绝缘氧化物层抛光到栅极结构的氮化物衬垫的水平面; 图案化和蚀刻绝缘氧化物层以暴露所述氮化物衬垫; 在所述第一侧壁间隔物上形成第二侧壁间隔物，所述第二侧壁间隔物包括厚度范围为约100至约400埃的氧化物层; 并且沉积和平坦化覆盖所述栅极结构和侧壁间隔物的多晶硅层。

55. 发明授权

US06410369B1 Soi-body selective link method and apparatus 失效
标题翻译：单体选择性联动方法及装置
公开(公告)号：US06410369B1
公开(公告)日：2002-06-25
申请号：US09591511
申请日：2000-06-12
申请人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
发明人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
IPC分类号： H01L2100
CPC分类号： H01L27/1104 , H01L27/1203
摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
摘要翻译：绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

56. 发明授权

US06404000B1 Pedestal collar structure for higher charge retention time in trench-type DRAM cells 失效
标题翻译：基座领结构，在沟槽式DRAM单元中具有更高的电荷保留时间
公开(公告)号：US06404000B1
公开(公告)日：2002-06-11
申请号：US09599261
申请日：2000-06-22
申请人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
发明人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.
摘要翻译：一种在衬底中形成有沟槽的存储器结构。环状氧化物位于沟槽的上部，并且包括基座部分。还公开了一种形成具有带衬垫环的环形氧化物的存储器件的方法。

57. 发明授权

US06288422B1 Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance 失效
标题翻译：用于制造具有垂直MOSFET和大沟槽电容的6F2 DRAM单元的结构和工艺
公开(公告)号：US06288422B1
公开(公告)日：2001-09-11
申请号：US09540276
申请日：2000-03-31
申请人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10891 , H01L29/945
摘要： A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.
摘要翻译： 6F2存储器单元结构，包括多个电容器，每个电容器位于衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的转移晶体管的多个，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个槽，所述槽以基本上均匀的间隔间隔开，所述多个条纹槽包括由每一个所述槽中的每一个填充有电介质材料构成的第一组槽，以及第二组槽是所述多个的剩余槽，所述第二组槽包含电介质材料，大阴影字线和大马士革字线触点; 连接到每个相应的栅极导体的相应字线电触头; 并且与每个位线扩散接触的位线，其中所述位线扩散具有由所述条纹槽的所述间隔限定的宽度，并且每个字线电触点与所述第二组槽的槽的边缘自对准。

58. 发明授权

US06259129B1 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06259129B1
公开(公告)日：2001-07-10
申请号：US09295133
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

59. 发明授权

US06255899B1 Method and apparatus for increasing interchip communications rates 失效
标题翻译：提高芯片间通信速率的方法和装置
公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译：提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

60. 发明授权

US06255158B1 Process of manufacturing a vertical dynamic random access memory device 失效
标题翻译：制造垂直动态随机存取存储器件的过程
公开(公告)号：US06255158B1
公开(公告)日：2001-07-03
申请号：US09667652
申请日：2000-09-22
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并且从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域，在所述第一扩散区域和所述第二扩散区域之间沿着所述沟槽的侧壁延伸的沟道区域，沿着从所述第一扩散区域延伸到所述第二扩散区域的所述沟槽的侧壁形成的栅极绝缘体，填充所述沟槽的栅极导体，具有顶表面，并且字线具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

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