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51. 发明授权

US06900488B1 Multi-cell organic memory element and methods of operating and fabricating 有权
标题翻译：多单元有机存储元件及其操作和制造方法
公开(公告)号：US06900488B1
公开(公告)日：2005-05-31
申请号：US10284946
申请日：2002-10-31
申请人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
发明人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
IPC分类号： H01L27/28 , H01L51/00 , H01L51/30 , H01L51/40 , H01L29/76
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0021 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.
摘要翻译：本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。

52. 发明授权

US06815340B1 Method of forming an electroless nucleation layer on a via bottom 有权
标题翻译：在通孔底部形成无电解成核层的方法
公开(公告)号：US06815340B1
公开(公告)日：2004-11-09
申请号：US10145928
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.
摘要翻译：制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物，以及使用合金在导电层的暴露部分上形成成核层。成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

53. 发明授权

US06773954B1 Methods of forming passive layers in organic memory cells 失效
标题翻译：在有机记忆细胞中形成钝化层的方法
公开(公告)号：US06773954B1
公开(公告)日：2004-08-10
申请号：US10313494
申请日：2002-12-05
申请人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
发明人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
IPC分类号： H01L5140
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/28 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0043 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.
摘要翻译：公开了在两个电极之间制造由具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。特别地，描述了形成电极和相邻钝化层的新颖方法。

54. 发明授权

US06538327B1 Method of copper interconnect formation using atomic layer copper deposition and a device thereby formed 有权
标题翻译：使用原子层铜沉积的铜互连形成方法和由此形成的器件
公开(公告)号：US06538327B1
公开(公告)日：2003-03-25
申请号：US10052831
申请日：2002-01-15
申请人： Sergey D. Lopatin , Carl Galewski , Takeshi T. N. Nogami
发明人： Sergey D. Lopatin , Carl Galewski , Takeshi T. N. Nogami
IPC分类号： H01L2940
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76873 , H01L21/76876 , H01L2221/1089
摘要： A method for fabricating a semiconductor interconnect structure having a substrate with an interconnect structure patterned therein, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer, and a device thereby formed. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.
摘要翻译：一种用于制造半导体互连结构的方法，该半导体互连结构具有其中构图的互连结构的衬底，阻挡层，预种子层，种子层，体互连层和密封层，以及由此形成的器件。使用原子层沉积技术形成阻挡层。随后，形成预种子层，以在阻挡层和预种子层之间产生异质外延界面。这是使用原子层外延技术来形成预种子层。此后，通过标准沉积技术形成种子层，以在种子和种子前层之间产生同质外延界面。在这种分层结构中，进行导电材料的进一步的大量沉积。从体层中除去过量的材料，并在顶部形成密封层以完成互连结构。

55. 发明授权

US06528884B1 Conformal atomic liner layer in an integrated circuit interconnect 有权
标题翻译：集成电路互连中的保形原子衬层
公开(公告)号：US06528884B1
公开(公告)日：2003-03-04
申请号：US09872328
申请日：2001-06-01
申请人： Sergey D. Lopatin , Minh Van Ngo
发明人： Sergey D. Lopatin , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/7681 , H01L21/76814 , H01L21/76838 , H01L21/76844 , H01L21/76862 , H01L21/76865 , H01L21/76876 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method, and an integrated circuit resulting therefrom has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the conductor and a conformal atomic liner is deposited in an atomic layer thickness to line the opening in the channel dielectric layer. A barrier layer is deposited over the conformal atomic liner and a seed layer is deposited over the barrier layer. A conductor core layer is deposited on the seed layer, filling the opening over the barrier layer and connecting to the semiconductor device.
摘要翻译：一种制造方法和由此产生的集成电路具有其上具有半导体器件的衬底。沟道电介质层沉积在器件上并具有设置在其中的开口。执行还原过程以减少导体上的氧化，并且以原子层厚度沉积保形原子衬垫以对通道介电层中的开口进行排列。阻挡层沉积在保形原子衬里上，并且在阻挡层上沉积种子层。导体芯层沉积在种子层上，填充阻挡层上的开口并连接到半导体器件。

56. 发明授权

US06518648B1 Superconductor barrier layer for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的超导体阻挡层
公开(公告)号：US06518648B1
公开(公告)日：2003-02-11
申请号：US09671944
申请日：2000-09-27
申请人： Sergey D. Lopatin
发明人： Sergey D. Lopatin
IPC分类号： H01L3900
CPC分类号： H01L21/76843 , H01L21/76891 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A high temperature superconductor material barrier layer lines the opening and a seed layer is deposited to line the superconductor material barrier layer. A seed layer and a conductor core fills the opening over the barrier layer to form a conductor channel. The superconductor material barrier layer can be of yttrium barium copper oxide deposited by a process, such as laser ablation (LA), chemical vapor deposition (CVD), atomic layer deposition (ALD), or self-ionized plasma (SIP) deposition on a low dielectric constant dielectric layer and having a copper seed layer deposited thereon by SIP deposition.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。高温超导体材料阻挡层对开口进行排列，沉积种子层以使超导体材料阻挡层成线。种子层和导体芯填充阻挡层上的开口以形成导体通道。超导体材料阻挡层可以是通过诸如激光烧蚀（LA），化学气相沉积（CVD），原子层沉积（ALD）或自离子等离子体（SIP）沉积的方法沉积的钇钡铜氧化物低介电常数介电层，并通过SIP沉积在其上沉积铜籽晶层。

57. 发明授权

US06465867B1 Amorphous and gradated barrier layer for integrated circuit interconnects 失效
标题翻译：用于集成电路互连的无定形和渐变阻挡层
公开(公告)号：US06465867B1
公开(公告)日：2002-10-15
申请号：US09792083
申请日：2001-02-21
申请人： Joffre F. Bernard , Sergey D. Lopatin
发明人： Joffre F. Bernard , Sergey D. Lopatin
IPC分类号： H01L2900
CPC分类号： H01L21/76846 , H01L21/76831 , H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口。已经植入复合材料的阻挡层对通道开口进行排列。导体芯填充阻挡层上的开口。阻挡层具有阻挡化合物的接近部分的介电层，其变化成纯屏障材料的导体芯的近似部分。

58. 发明授权

US06368965B1 Method for low stress plating of semiconductor vias and channels 有权
标题翻译：半导体通孔和通道的低应力电镀方法
公开(公告)号：US06368965B1
公开(公告)日：2002-04-09
申请号：US09784842
申请日：2001-02-15
申请人： Sergey D. Lopatin
发明人： Sergey D. Lopatin
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/76877
摘要： A method is provided for forming conductive layers in semiconductor device channels and vias by using forward current and periodic pulse reverses for filling inward from the sidewalls of the channels and vias. The pulse reversals and inward filling reduce recrystallization rate to improve electromigration resistance and reduce the stress in the conductive layers to eliminate voids.
摘要翻译：提供了一种用于在半导体器件沟道和通孔中形成导电层的方法，其中使用正向电流和周期性脉冲反转来从通道和通孔的侧壁向内填充。脉冲反转和向内填充减少再结晶速率，以提高电迁移阻力，并减少导电层中的应力以消除空隙。

59. 发明授权

US06368954B1 Method of copper interconnect formation using atomic layer copper deposition 有权
标题翻译：使用原子层铜沉积的铜互连形成方法
公开(公告)号：US06368954B1
公开(公告)日：2002-04-09
申请号：US09627352
申请日：2000-07-28
申请人： Sergey D. Lopatin , Carl Galewski , Takeshi T. N. Nogami
发明人： Sergey D. Lopatin , Carl Galewski , Takeshi T. N. Nogami
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76873 , H01L21/76876 , H01L2221/1089
摘要： A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.
摘要翻译：一种半导体互连结构，其具有在其上图案化的互连结构的衬底，阻挡层，预种子层，种子层，体互连层和密封层。描述了用于创建这种结构的过程。使用原子层沉积技术形成阻挡层。随后，形成预种子层，以在阻挡层和预种子层之间产生异质外延界面。这是使用原子层外延技术来形成预种子层。此后，通过标准沉积技术形成种子层，以在种子和种子前层之间产生同质外延界面。在这种分层结构中，进行导电材料的进一步的大量沉积。从体层中除去过量的材料，并在顶部形成密封层以完成互连结构。

60. 发明授权

US09240585B2 Manufacturing of high capacity prismatic lithium-ion alloy anodes 有权
标题翻译：大容量棱柱形锂离子合金阳极的制造
公开(公告)号：US09240585B2
公开(公告)日：2016-01-19
申请号：US14001826
申请日：2012-02-28
申请人： Sergey D. Lopatin , Dmitri A. Brevnov , Eric H. Liu , Robert Z. Bachrach , Connie P. Wang
发明人： Sergey D. Lopatin , Dmitri A. Brevnov , Eric H. Liu , Robert Z. Bachrach , Connie P. Wang
IPC分类号： H01M4/13 , H01M4/04 , H01M4/02 , H01M4/134 , H01M4/1395 , H01M4/36 , H01M4/38 , H01M4/64 , H01M4/62 , H01M4/66
CPC分类号： H01M4/626 , H01M4/02 , H01M4/0404 , H01M4/0419 , H01M4/0452 , H01M4/134 , H01M4/1395 , H01M4/364 , H01M4/366 , H01M4/38 , H01M4/386 , H01M4/587 , H01M4/625 , H01M4/64 , H01M4/661 , H01M10/0525 , H01M2004/021 , H01M2004/027 , Y02E60/122 , Y02P70/54
摘要： High capacity energy storage devices and energy storage device components, and more specifically, to a system and method for fabricating such high capacity energy storage devices and storage device components using processes that form three-dimensional porous structures are provided. In one embodiment, an anode structure for use in a high capacity energy storage device, comprising a conductive collector substrate, a three-dimensional copper-tin-iron porous conductive matrix formed on one or more surfaces of the conductive collector substrate, comprising a plurality of meso-porous structures formed over the conductive current collector, and an anodically active material deposited over the three-dimensional copper-tin-iron porous conductive matrix is provided. In certain embodiments, the three-dimensional copper-tin-iron porous conductive matrix further comprises a plurality of columnar projections formed on the conductive current collector with the plurality of meso-porous structure formed on the plurality of columnar projections.
摘要翻译：更具体地，涉及一种使用形成三维多孔结构的工艺来制造这种高容量能量存储装置和存储装置部件的系统和方法。在一个实施例中，一种用于高容量能量存储装置的阳极结构，包括导电收集器基板，形成在导电集电基板的一个或多个表面上的三维铜 - 锡 - 铁多孔导电基体，包括多个提供了形成在导电集电器上的中孔多孔结构，以及沉积在三维铜 - 锡 - 铁多孔导电基体上的阳极活性材料。在某些实施例中，三维铜 - 锡 - 铁多孔导电基体还包括形成在导电集电器上的多个柱状突起，其中多个中孔多孔结构形成在多个柱状突起上。

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