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51. 发明申请

US20080017890A1 Highly dense monolithic three dimensional memory array and method for forming 审中-公开
标题翻译：高密度单片三维记忆阵列及其形成方法
公开(公告)号：US20080017890A1
公开(公告)日：2008-01-24
申请号：US11479697
申请日：2006-06-30
申请人： Jack Yuan , George Samachisa
发明人： Jack Yuan , George Samachisa
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/1021 , H01L27/24
摘要： A method to form a highly dense monolithic three dimensional memory array is provided. In preferred embodiments, conductive or semiconductor spacers can be formed, then used as hard masks to pattern underlying layers, forming features at sublithographic pitch. Methods of the invention minimize photomasking steps and thus simplify fabrication.
摘要翻译：提供了一种形成高密度单片三维存储器阵列的方法。在优选实施例中，可以形成导电或半导体间隔物，然后用作硬掩模来图案化下层，以亚光刻间距形成特征。本发明的方法使光掩模步骤最小化，从而简化制造。

52. 发明申请

US20070217264A1 Substrate Electron Injection Techniques for Programming Non-Volatile Charge Storage Memory Cells 有权
标题翻译：用于编程非易失性电荷存储单元的基板电子注入技术
公开(公告)号：US20070217264A1
公开(公告)日：2007-09-20
申请号：US11750469
申请日：2007-05-18
申请人： George Samachisa
发明人： George Samachisa
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483
摘要： A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.
摘要翻译：用于闪速存储器的编程技术使电子从衬底注入到存储器单元的电荷存储元件中。沿着公共字线或其他公共控制栅极线的存储器单元的源极和漏极区域被施加到公共线路上的电压编程，使得电浮动，而不被编程的存储器单元的源极和漏极区域施加电压。该编程技术被应用于具有NOR或NAND架构的大型存储器单元阵列。

53. 发明申请

US20060227620A1 Non-Volatile Memory Cells Utilizing Substrate Trenches 有权
标题翻译：非易失性记忆单元利用基底沟槽
公开(公告)号：US20060227620A1
公开(公告)日：2006-10-12
申请号：US11423121
申请日：2006-06-08
申请人： Eliyahou Harari , Jack Yuan , George Samachisa , Henry Chien
发明人： Eliyahou Harari , Jack Yuan , George Samachisa , Henry Chien
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L27/11553
摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.
摘要翻译：描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。第三个门提供擦除或转向功能。在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

54. 发明申请

US20060023507A1 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US20060023507A1
公开(公告)日：2006-02-02
申请号：US11238911
申请日：2005-09-28
申请人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C7/10 , G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

55. 发明申请

US20050157551A1 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US20050157551A1
公开(公告)日：2005-07-21
申请号：US11075427
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

56. 发明授权

US06762092B2 Scalable self-aligned dual floating gate memory cell array and methods of forming the array 有权
标题翻译：可扩展自对准双浮栅存储单元阵列和形成阵列的方法
公开(公告)号：US06762092B2
公开(公告)日：2004-07-13
申请号：US09925102
申请日：2001-08-08
申请人： Jack H. Yuan , Eliyahou Harari , Yupin K. Fong , George Samachisa
发明人： Jack H. Yuan , Eliyahou Harari , Yupin K. Fong , George Samachisa
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11531 , H01L27/11548 , H01L29/42328 , H01L29/7887
摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.
摘要翻译：通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路个别浮动门。衬底中的电荷源和漏极扩散在整个行中连续延伸。沉积在浮动栅极行之间的场电介质在行之间提供电隔离。可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

57. 发明授权

US06532172B2 Steering gate and bit line segmentation in non-volatile memories 有权
标题翻译：非易失性存储器中的转向门和位线分割
公开(公告)号：US06532172B2
公开(公告)日：2003-03-11
申请号：US09871333
申请日：2001-05-31
申请人： Eliyahou Harari , George Samachisa , Daniel C. Guterman , Jack H. Yuan
发明人： Eliyahou Harari , George Samachisa , Daniel C. Guterman , Jack H. Yuan
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C7/12 , G11C16/0433 , G11C16/0458 , G11C16/0491
摘要： Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.
摘要翻译：转向和位线（例如，闪存EEPROM系统）沿着存储单元阵列的列进行分段。在一个实施例中，其一个段的转向和位线一次连接到相应的全局转向和位线。包括在各个转向门段中的存储单元的行数是单个位线段中包括的行数的倍数，以便具有较少的转向门段。这通过减少转向门所需的段选择晶体管的数量来节省相当大的电路面积，因为这些晶体管必须大于用于选择位线段以用于处理较高电压的晶体管。在另一个实施例中，组合本地导向门线段以便减少它们的数量，然后每个段的减少的数量直接与地址解码器相连，而不需要在解码器之外的多个大的开关晶体管来选择该段。

58. 发明授权

US06266278B1 Dual floating gate EEPROM cell array with steering gates shared adjacent cells 有权
标题翻译：具有转向门的双浮栅EEPROM单元阵列共享相邻单元
公开(公告)号：US06266278B1
公开(公告)日：2001-07-24
申请号：US09634694
申请日：2000-08-08
申请人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
发明人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115
摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.
摘要翻译：具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。双门单元增加了可以存储的数据的密度。不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。因此，转向门由不同但相邻的存储单元的两个浮动门共享。在一个阵列实施例中，浮动栅极形成在基板的表面上，其中增加的转向门的宽度使得它们更容易形成，作为对阵列的缩小的限制，将它们移除，因为它们的尺寸较小，因此需要更少的沿着它们的长度的电触点，因为增加电导，更容易接触，并减少与它们连接所需的导电迹线的数量。在将浮动栅极擦除到选择栅极而不是衬底的阵列中，较宽的转向栅极有利地使其从选择栅极覆盖的扩散分离。单个转向门用于两个浮动栅极的这种使用也允许浮动栅极在另一个实施例中形成在衬底中的沟槽的侧壁上，其间具有公共转向栅极，以进一步增加数据的密度存储。多个数据位也可以存储在每个浮动门上。

59. 发明授权

US6103573A Processing techniques for making a dual floating gate EEPROM cell array 有权
公开(公告)号：US6103573A
公开(公告)日：2000-08-15
申请号：US343493
申请日：1999-06-30
申请人： Eliyahou Harari , Jack H. Yuan , George Samachisa
发明人： Eliyahou Harari , Jack H. Yuan , George Samachisa
IPC分类号： H01L21/336 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L29/66825 , H01L29/7887
摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. Processing methods of forming such a cell array include two etching steps to separate strips of conductive material into individual floating gates that are self-aligned with source/drain diffusions and other gate elements. In one embodiment, this is accomplished by two etching steps with separate masks. In another embodiment, a reference dielectric mask is first formed over the conductive material layer strips and used as a reference for two etching masks that are aligned with each other. In a further embodiment, isolation of the memory cells is provided in the column direction by forming rectangular trenches in the substrate between cells that are filled with dielectric. Specific processing techniques also have applications to form single floating gate EEPROM cell arrays, other types of memory cells and integrated circuit elements.

60. 发明授权

US6091633A Memory array architecture utilizing global bit lines shared by multiple cells 有权
标题翻译：利用由多个单元共享的全局位线的存储器阵列架构
公开(公告)号：US6091633A
公开(公告)日：2000-07-18
申请号：US370775
申请日：1999-08-09
申请人： Raul-Adrian Cernea , George Samachisa
发明人： Raul-Adrian Cernea , George Samachisa
IPC分类号： G11C7/18 , G11C16/04
CPC分类号： G11C7/18 , G11C16/0441
摘要： As a specific application of a new memory architecture, an array of non-volatile dual floating gate memory cells is arranged on a semiconductor substrate with global bit lines extending in a column direction that are either permanently connected, or connectable through transistor switches, to short source and drain diffusions that are oriented in the row direction between the global bit lines. Multiple columns of memory cells are positioned between the global bit lines. Bit selection lines oriented in the column direction are connected to the gates of select transistors within the memory cells. Word lines individually extend over one or two rows of floating gates. This arrangement provides a very small array that allows for future scaling. It also enables the use of metal lines strapped to the global bit line diffusions, and to polysilicon word lines to reduce their resistance, without imposing their larger pitch on other array elements.
摘要翻译：作为新存储器架构的具体应用，非易失性双浮栅存储器单元的阵列被布置在半导体衬底上，其全局位线沿列方向延伸，永久连接或通过晶体管开关可连接到短路在全局位线之间的行方向上定向的源极和漏极扩散。多列存储器单元位于全局位线之间。在列方向上定向的位选择线连接到存储单元内的选择晶体管的栅极。字线分别延伸一行或两行浮动门。这种安排提供了一个非常小的数组，可以进行未来的缩放。它还可以使用捆绑到全局位线扩散的金属线，以及多晶硅字线以减少其电阻，而不会在其他阵列元件上施加较大的间距。

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