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51. 发明申请

US20070007327A1 Rotary punching apparatus 失效
标题翻译：旋转冲孔机
公开(公告)号：US20070007327A1
公开(公告)日：2007-01-11
申请号：US11334815
申请日：2006-01-18
申请人： Ok-Hwan Kim , Sang-Ho Lee
发明人： Ok-Hwan Kim , Sang-Ho Lee
IPC分类号： B26D7/01
CPC分类号： B26F1/36 , B26D3/10 , B26D7/2628 , B26D2007/0056 , B26D2007/0087 , B26F1/02 , B26F1/14 , B26F1/32 , B26F1/46 , Y10T83/8785 , Y10T83/8831 , Y10T83/8841 , Y10T83/943 , Y10T83/944
摘要： Rotary punching apparatus includes: an upper rotation plate provided with punching member on which punching blade having a pattern of a specific shape is formed, and an upper jig which support elastically the punching member and forms a guide hole in the same shape as the pattern; an upper plate configured to enable the upper rotation plate to be rotated; a lower rotation plate including lower jig on which a punching hole in the same shape as the pattern is formed; and lower plate configured to enable the lower rotation plate to be rotated. The upper and the lower plate are provided with at least one magnets in a position opposite to each other and the upper and the lower rotation plate are provided with at least one or more magnets in a position opposite to each other, so that the fixed position is mutually aligned due to the magnetic force of the magnet. As a result, the present invention can freely punch a desired position irrespective of punching positions such as the seat as an object of the punching.
摘要翻译：旋转冲孔装置包括：上旋转板，其上形成有形成具有特定形状的图案的冲压刀片的冲压构件;弹性地支撑冲压构件并形成与图案相同形状的引导孔的上夹具; 配置成使上部旋转板旋转的上板; 下部旋转板包括下部夹具，其上形成与图案相同形状的冲孔; 并且下板被配置为使得下旋转板能够旋转。上板和下板在彼此相对的位置设置有至少一个磁体，并且上下旋转板在彼此相对的位置中设置有至少一个或多个磁体，使得固定位置由于磁体的磁力而相互对准。结果，本发明可以自由地冲压期望的位置，而不管冲孔位置如作为冲孔的对象的座。

52. 发明授权

US06670253B2 Fabrication method for punch-through defect resistant semiconductor memory device 有权
公开(公告)号：US06670253B2
公开(公告)日：2003-12-30
申请号：US10265723
申请日：2002-10-08
申请人： Sang-Ho Lee
发明人： Sang-Ho Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , H01L27/10873 , H01L29/0653 , H01L29/41766
摘要： A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.

53. 发明授权

US06483158B1 Semiconductor memory device and fabrication method therefor 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06483158B1
公开(公告)日：2002-11-19
申请号：US09481495
申请日：2000-01-12
申请人： Sang-Ho Lee
发明人： Sang-Ho Lee
IPC分类号： H01L2976
CPC分类号： H01L29/66636 , H01L27/10873 , H01L29/0653 , H01L29/41766
摘要： A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.
摘要翻译：半导体器件及其制造方法，其可以例如通过在半导体衬底中的源极/漏极区域周围形成氧化物间隔来防止穿通而不是形成常规的卤素离子注入层。这样的结构例如通过减小结电容来提高操作速度，通过削弱漏极区域周围的电场来防止热载流子效应的发生，并且通过防止发生闩锁来提高可靠性。半导体器件包括形成在半导体衬底上的栅极电极，形成在栅极侧壁处的侧壁间隔物，形成在半导体衬底中的每个侧壁间隔物下方的杂质层，形成在栅极两侧的半导体衬底中的沟槽电极，形成在每个沟槽的底部内角处的氧化物间隔物，以及填充每个沟槽的导电材料。

54. 发明授权

US5937283A Method of making a dual gate trench thin film transistor 失效
标题翻译：制造双栅沟槽薄膜晶体管的方法
公开(公告)号：US5937283A
公开(公告)日：1999-08-10
申请号：US974281
申请日：1997-11-19
申请人： Sang-Ho Lee
发明人： Sang-Ho Lee
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/70
CPC分类号： H01L29/78645 , H01L27/1214 , H01L29/66757 , H01L29/78624 , H01L29/78642
摘要： A thin film transistor and a method for fabricating the same in which a self alignment method is used to form an offset area and source and drain electrodes are disclosed, the TFT including a substrate; a trench formed in the substrate,; an active layer fromed on the substrate and on the trench; a gate insulating film formed on the active layer; a gate electrode formed on the gate insulating film on at least one side of the trench; a source region formed in the active layer on a bottom side of the trench; and drain regions formed in the active layer on the substrate to be isolated form the gate electrode.
摘要翻译：公开了一种薄膜晶体管及其制造方法，其中使用自对准方法来形成偏移区域和源极和漏极，所述TFT包括衬底; 形成在衬底中的沟槽; 在衬底上和沟槽上的有源层; 形成在有源层上的栅极绝缘膜; 在所述沟槽的至少一侧上形成在所述栅极绝缘膜上的栅电极; 形成在所述沟槽的底侧上的所述有源层中的源极区域; 以及形成在待隔离的基板上的有源层中的漏极区域形成栅电极。

55. 发明授权

US5777945A Column decoding circuit for semiconductor memory device 失效
标题翻译：用于半导体存储器件的列解码电路
公开(公告)号：US5777945A
公开(公告)日：1998-07-07
申请号：US886445
申请日：1997-07-01
申请人： Jae-Kwang Sim , Sang-Ho Lee
发明人： Jae-Kwang Sim , Sang-Ho Lee
IPC分类号： G11C11/413 , G11C8/10 , G11C11/407 , G11C11/409 , H03M1/66 , G11C8/00
CPC分类号： G11C8/10
摘要： A column decoding circuit for a semiconductor memory device includes a decoding unit and a pulse generating unit. The decoding unit decodes a selected column address and generates a selection signal. The pulse generating unit self-generates a pulse signal based on the selection signal output from the decoding unit. The pulse generating unit uses the self-generated pulse signal and the selection signal to output to a selected column switch a control signal having a minimum pulse width sufficient for selecting an associated column. Accordingly, a high speed read operation is performed by decreasing a loading and transmission time of the control signal. Further, power consumption of the column decoding circuit is decreased by self-generating the pulse signal, preferably based on the selection signal.
摘要翻译：用于半导体存储器件的列解码电路包括解码单元和脉冲产生单元。解码单元解码所选择的列地址并产生选择信号。脉冲发生单元基于从解码单元输出的选择信号自生成脉冲信号。脉冲发生单元使用自生成的脉冲信号，并且选择信号输出到选定的列切换具有足以选择相关列的最小脉冲宽度的控制信号。因此，通过减小控制信号的负载和发送时间来执行高速读取操作。此外，优选地基于选择信号，通过自发生脉冲信号来降低列解码电路的功耗。

56. 发明授权

US08810018B2 Stacked integrated circuit package system with face to face stack configuration 有权
标题翻译：堆叠集成电路封装系统，具有面对面堆叠配置
公开(公告)号：US08810018B2
公开(公告)日：2014-08-19
申请号：US11307382
申请日：2006-02-03
申请人： Jong-Woo Ha , Sang-Ho Lee , Soo-San Park
发明人： Jong-Woo Ha , Sang-Ho Lee , Soo-San Park
IPC分类号： H01L23/02
CPC分类号： H01L24/48 , H01L23/3128 , H01L24/85 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05599 , H01L2224/131 , H01L2224/16 , H01L2224/274 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/85051 , H01L2224/85399 , H01L2224/85986 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/85186 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： A stacked integrated circuit package system is provided forming a first molded chip comprises attaching a conductor on a wafer, applying an encapsulant around the conductor, and exposing a surface of the conductor in the encapsulant, attaching a first electrical interconnect on the conductor of the first molded chip and stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.
摘要翻译：提供了一种堆叠的集成电路封装系统，其形成第一模制芯片，包括将导体附着在晶片上，在导体周围施加密封剂，以及将导体的表面暴露在密封剂中，将第一电互连件附接到第一将第一模制芯片上的集成电路器件堆叠在一起，其中集成电路器件的电连接器通过第一电互连连接到第一模制芯片的导体上。

57. 发明授权

US08692365B2 Integrated circuit packaging system with thermal dispersal structures and method of manufacture thereof 有权
标题翻译：具有散热结构的集成电路封装系统及其制造方法
公开(公告)号：US08692365B2
公开(公告)日：2014-04-08
申请号：US13163611
申请日：2011-06-17
申请人： DongSoo Moon , Taewoo Lee , Soo-San Park , SooMoon Park , Sang-Ho Lee
发明人： DongSoo Moon , Taewoo Lee , Soo-San Park , SooMoon Park , Sang-Ho Lee
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L23/36 , H01L23/49833 , H01L24/48 , H01L24/73 , H01L25/03 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation.
摘要翻译：一种制造集成电路封装系统的方法，包括：提供基底; 将具有接触垫的包装堆叠组件附接在所述基底基板上; 将具有锥形侧的空腔的封装直接施加在封装堆叠组件上方，该接触垫暴露在空腔中; 将凹陷的电路单元附接在所述空腔和所述接触垫上，所述凹腔由所述凹陷电路单元和所述空腔的锥形侧形成; 并将热结构安装在凹进的电路单元，空腔和封装之上。

58. 发明授权

US08632909B2 Sheath for enclosing a pouch of a secondary battery 有权
标题翻译：用于封装二次电池的护套
公开(公告)号：US08632909B2
公开(公告)日：2014-01-21
申请号：US11407350
申请日：2006-04-20
申请人： Sang-Ho Lee
发明人： Sang-Ho Lee
IPC分类号： H01M2/04
CPC分类号： H01M2/1022 , H01M2/0212 , H01M2/0267 , H01M2/0275 , H01M2/0277 , H01M2/0285 , H01M2/1066 , H01M10/0436 , H01M10/052
摘要： A secondary battery includes an electrode assembly having first and second electrodes and a separator, a pouch type case for receiving the electrode assembly, and a sheath for enclosing outer sides of the case. The sheath can prevent damage to the pouch in electronic devices to which the secondary battery is applicable as an inner pack type.
摘要翻译：二次电池包括具有第一和第二电极和隔板的电极组件，用于容纳电极组件的袋状壳体和用于封闭壳体的外侧的护套。护套可以防止二次电池作为内包装类型的电子设备中的小袋损坏。

59. 发明授权

US08390110B2 Integrated circuit packaging system with cavity and method of manufacture thereof 有权
标题翻译：具有空腔的集成电路封装系统及其制造方法
公开(公告)号：US08390110B2
公开(公告)日：2013-03-05
申请号：US12582582
申请日：2009-10-20
申请人： Sang-Ho Lee , Taewoo Lee , Soo-San Park
发明人： Sang-Ho Lee , Taewoo Lee , Soo-San Park
IPC分类号： H01L23/48
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L24/16 , H01L24/29 , H01L24/48 , H01L24/85 , H01L25/03 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83191 , H01L2224/85001 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01327 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/18165 , H01L2924/19041 , H01L2924/19107 , H01L2924/3025 , H01L2224/85 , H01L2224/83 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A method of manufacture of an integrated circuit packaging system includes: mounting a substrate-less integrated circuit package, having a terminal having characteristics of an intermetallic compound, over a substrate; connecting the substrate and the substrate-less integrated circuit package; and forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed.
摘要翻译：一种集成电路封装系统的制造方法，包括：在衬底上安装具有金属间化合物特性的端子的无基板集成电路封装; 连接基板和无基板集成电路封装; 以及在所述无衬底的集成电路封装上形成基底封装，所述端子暴露。

60. 发明授权

US08383458B2 Integrated circuit package system employing an offset stacked configuration and method for manufacturing thereof 有权
标题翻译：采用偏移堆叠结构的集成电路封装系统及其制造方法
公开(公告)号：US08383458B2
公开(公告)日：2013-02-26
申请号：US12974265
申请日：2010-12-21
申请人： DaeSik Choi , BumJoon Hong , Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
发明人： DaeSik Choi , BumJoon Hong , Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L24/81 , H01L23/552 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/03 , H01L25/105 , H01L2224/1134 , H01L2224/131 , H01L2224/16225 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81194 , H01L2224/81801 , H01L2224/83 , H01L2224/8592 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00013 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H01L2924/00014 , H01L2224/13099 , H01L2924/00012 , H01L2924/00011 , H01L2924/00
摘要： A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect.
摘要翻译：一种用于制造集成电路封装系统的方法，包括：通过在一侧形成的电互连，提供包括耦合到基底基板的第一集成电路的基底封装; 以及将偏移封装安装在所述基底封装上，所述偏移封装通过系统互连电耦合到所述基底衬底。

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