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51. 发明申请

US20190122891A1 METHOD OF FORMING MULTI-THRESHOLD VOLTAGE DEVICES AND DEVICES SO FORMED 审中-公开
公开(公告)号：US20190122891A1
公开(公告)日：2019-04-25
申请号：US15898420
申请日：2018-02-16
申请人： Samsung Electronics Co., Ltd.
发明人： Wei-E Wang , Mark S. Rodder , Borna J. Obradovic
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/28158 , H01L21/28088 , H01L21/823437 , H01L21/823462 , H01L21/823828 , H01L21/823857 , H01L27/088 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

52. 发明申请

US20180286764A1 FIELD EFFECT TRANSISTOR WITH STACKED NANOWIRE-LIKE CHANNELS AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180286764A1
公开(公告)日：2018-10-04
申请号：US15997596
申请日：2018-06-04
申请人： Samsung Electronics Co., Ltd.
发明人： Mark S. Rodder , Borna J. Obradovic
IPC分类号： H01L21/8238 , H01L29/786 , H01L29/423 , H01L29/06 , H01L21/02 , H01L27/092
CPC分类号： H01L21/823807 , B82Y10/00 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/84 , H01L27/04 , H01L27/092 , H01L27/0924 , H01L27/1203 , H01L29/0673 , H01L29/42364 , H01L29/42384 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78618 , H01L29/78696
摘要： A field effect transistor includes a fin having a stack of nanowire-like channel regions including at least first and a second nanowire-like channel regions, source and drain electrodes on opposite sides of the fin, a dielectric separation region including a dielectric material between the first and second nanowire-like channel regions, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer of the gate stack does not extend between the first and second nanowire-like channel regions.

53. 发明申请

US20180174034A1 HIGH-DENSITY NEUROMORPHIC COMPUTING ELEMENT 审中-公开
公开(公告)号：US20180174034A1
公开(公告)日：2018-06-21
申请号：US15488419
申请日：2017-04-14
申请人： Samsung Electronics Co., Ltd.
发明人： Borna J. Obradovic , Titash Rakshit , Mark S. Rodder
IPC分类号： G06N3/063 , H01L29/808 , H01L29/66
CPC分类号： G06N3/0635 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/66825 , H01L29/7881 , H01L29/8083
摘要： A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

54. 发明授权

US09831323B2 Structure and method to achieve compressively strained Si NS 有权
公开(公告)号：US09831323B2
公开(公告)日：2017-11-28
申请号：US15267134
申请日：2016-09-15
申请人： Samsung Electronics Co., Ltd.
发明人： Jorge A. Kittl , Ganesh Hegde , Robert Christopher Bowen , Borna J. Obradovic , Mark S. Rodder
IPC分类号： H01L29/78 , H01L29/66 , H01L29/201 , H01L29/06 , H01L21/02 , H01L21/306 , H01L21/04 , H01L21/465
CPC分类号： H01L29/6681 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02485 , H01L21/02532 , H01L21/02603 , H01L21/0475 , H01L21/30604 , H01L21/465 , H01L29/0673 , H01L29/66439 , H01L29/6653 , H01L29/66553 , H01L29/7848 , H01L29/7853
摘要： A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

55. 发明申请

US20170098661A1 SEMICONDUCTOR DEVICE INCLUDING A REPEATER/BUFFER AT HIGHER METAL ROUTING LAYERS AND METHODS OF MANUFACTURING THE SAME 有权
公开(公告)号：US20170098661A1
公开(公告)日：2017-04-06
申请号：US15210867
申请日：2016-07-14
申请人： Samsung Electronics Co., Ltd.
发明人： Titash Rakshit , Borna J. Obradovic , Rwik Sengupta , Wei-E Wang , Ryan Hatcher , Mark S. Rodder
IPC分类号： H01L27/12 , H01L23/528 , H01L29/24 , H01L29/10 , H01L29/78 , H01L29/423 , H01L29/66 , H01L21/84 , H01L23/522 , H01L29/45
CPC分类号： H01L27/12 , H01L21/84 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L29/1033 , H01L29/24 , H01L29/42376 , H01L29/45 , H01L29/66969 , H01L29/78 , H01L29/78681
摘要： A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

56. 发明授权

US09583590B2 Integrated circuit devices including FinFETs and methods of forming the same 有权
标题翻译：包括FinFET的集成电路器件及其形成方法
公开(公告)号：US09583590B2
公开(公告)日：2017-02-28
申请号：US14698402
申请日：2015-04-28
申请人： Samsung Electronics Co., Ltd.
发明人： Borna J. Obradovic , Robert C. Bowen , Mark S. Rodder
IPC分类号： H01L29/66 , H01L21/82 , H01L21/8234 , H01L21/8238 , H01L21/308 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66522 , H01L21/3086 , H01L21/823431 , H01L21/823821 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.
摘要翻译：提供了形成finFET的方法。所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域源/漏区。源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

57. 发明申请

US20160111284A1 STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET 审中-公开
标题翻译：应变堆叠的纳米晶体管和/或量子堆积的纳米硅片
公开(公告)号：US20160111284A1
公开(公告)日：2016-04-21
申请号：US14918954
申请日：2015-10-21
申请人： Samsung Electronics Co., Ltd.
发明人： Jorge A. Kittl , Borna J. Obradovic , Robert C. Bowen , Mark S. Rodder
IPC分类号： H01L21/02 , H01L29/06 , H01L29/10 , H01L21/283 , H01L21/306
CPC分类号： H01L29/0669 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L29/0665 , H01L29/1054 , H01L29/7781 , H01L29/7782 , H01L29/7783
摘要： Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.
摘要翻译：示例性实施例提供制造具有一个或多个子堆叠的纳米片堆叠结构。示例性实施例的方面包括：生长一个或多个子堆叠的外延晶体初始堆叠，每个子堆叠具有至少三个层，牺牲层A和至少两个不同的非牺牲层B和C 具有不同的材料性质，其中非牺牲层B和C层保持低于在所有加工期间对应于亚稳态的热力学或动力学临界厚度，并且其中牺牲层An仅被放置在每个的顶部或底部并且每个子堆叠使用牺牲层A之一连接到顶部或底部的相邻子堆叠; 继续纳米片装置的制造流程，使得在外延晶体堆叠的每个端部处形成柱结构，以在选择性蚀刻牺牲层之后将纳米片保持在适当位置; 并且将牺牲层A选择性地去除所有非牺牲层B和C，而堆叠中的其余层被柱结构保持就位，使得在去除牺牲层An之后，每个子堆包含非牺牲层 - 层B和C.

58. 发明授权

US09112130B2 Quantum interference based logic devices including electron monochromator 有权
标题翻译：基于量子干涉的逻辑器件包括电子单色仪
公开(公告)号：US09112130B2
公开(公告)日：2015-08-18
申请号：US14478344
申请日：2014-09-05
申请人： Samsung Electronics Co., Ltd.
发明人： Borna J. Obradovic , Robert C. Bowen
IPC分类号： H03K19/195 , H01L49/00 , H01L29/16 , H01L29/20 , H01L29/88 , H01L29/06
CPC分类号： H01L49/006 , H01L29/0669 , H01L29/1606 , H01L29/20 , H01L29/88
摘要： A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.
摘要翻译：提供了一种包括电子单色仪的逻辑器件。电子单色仪包括设置在第一和第二隧道势垒之间的量子点，耦合到第一隧道势垒的发射极和耦合到第二隧穿势垒的集电极。逻辑器件还包括量子干涉器件。量子干涉装置包括耦合到电子单色仪的集电极的源。

59. 发明申请

US20150123701A1 QUANTUM INTERFERENCE BASED LOGIC DEVICES INCLUDING ELECTRON MONOCHROMATOR 有权
标题翻译：基于量子干扰的逻辑器件，包括电子单色器
公开(公告)号：US20150123701A1
公开(公告)日：2015-05-07
申请号：US14478344
申请日：2014-09-05
申请人： Samsung Electronics Co., Ltd.
发明人： Borna J. Obradovic , Robert C. Bowen
IPC分类号： H01L49/00 , H01L29/06 , H01L29/88 , H01L29/16 , H01L29/20
CPC分类号： H01L49/006 , H01L29/0669 , H01L29/1606 , H01L29/20 , H01L29/88
摘要： A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.
摘要翻译：提供了一种包括电子单色仪的逻辑器件。电子单色仪包括设置在第一和第二隧道势垒之间的量子点，耦合到第一隧道势垒的发射极和耦合到第二隧穿势垒的集电极。逻辑器件还包括量子干涉器件。量子干涉装置包括耦合到电子单色仪的集电极的源。

60. 发明申请

US20150123215A1 CRYSTALLINE MULTIPLE-NANOSHEET III-V CHANNEL FETS 有权
标题翻译：晶体多层纳米III-V通道FET
公开(公告)号：US20150123215A1
公开(公告)日：2015-05-07
申请号：US14270690
申请日：2014-05-06
申请人： Samsung Electronics Co., Ltd.
发明人： Borna J. Obradovic , Jorge A. Kittl , Mark S. Rodder
IPC分类号： H01L29/10 , H01L29/78 , H01L29/51 , H01L29/20 , H01L29/49
CPC分类号： H01L29/42392 , H01L29/78681 , H01L29/78696
摘要： A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.
摘要翻译：场效应晶体管包括其中包括晶体半导体沟道区的主体层，以及沟道区上的栅叠层。栅极堆叠包括晶体半导体栅极层和栅极层和沟道区之间的晶体半导体栅极介电层。还讨论了相关设备和制造方法。

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