专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US4999519A Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier 失效
标题翻译：具有低功耗的半导体电路具有发射极耦合逻辑或差分放大器
公开(公告)号：US4999519A
公开(公告)日：1991-03-12
申请号：US277992
申请日：1988-11-30
申请人： Goro Kitsukawa , Kazumasa Yanagisawa , Takayuki Kawahara , Ryoichi Hori , Yoshinobu Nakagome , Noriyuki Hamma , Kiyoo Itoh , Hiromi Tukada
发明人： Goro Kitsukawa , Kazumasa Yanagisawa , Takayuki Kawahara , Ryoichi Hori , Yoshinobu Nakagome , Noriyuki Hamma , Kiyoo Itoh , Hiromi Tukada
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： An ECL circuit wherein a current switch and an emitter follower are coupled, is so constructed that, in a standby mode, the current switch has its current cut off or rendered smaller than in an operating mode. In addition, the ECL circuit comprises means for decoupling a load resistance of the current switch and a base of the emitter follower in the case of cutting off the current of the current switch, or means for increasing the load resistance of the current switch in the case of rendering the current of the current switch smaller. The semiconductor circuit of the present invention can reduce the power consumption of the ECL circuit and can suppress fluctuations in the voltage levels of the outputs of the ECL circuit.
摘要翻译：其中电流开关和射极跟随器耦合的ECL电路被构造成使得在待机模式中，电流开关的电流切断或变得比操作模式小。此外，ECL电路包括在切断电流开关的电流的情况下解耦电流开关的负载电阻和射极跟随器的基极的装置，或用于增加电流开关的负载电阻的装置使当前开关的电流变小的情况。本发明的半导体电路可以降低ECL电路的功耗，并且可以抑制ECL电路的输出的电压电平的波动。

52. 发明授权

US4965769A Semiconductor memory capable of high-speed data erasing 失效
标题翻译：具有高速数据擦除功能的半导体存储器
公开(公告)号：US4965769A
公开(公告)日：1990-10-23
申请号：US278025
申请日：1988-11-30
申请人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
发明人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12 , G11C11/404 , G11C11/4072 , G11C11/408 , H01L27/10
CPC分类号： G11C7/20 , G11C11/4072 , G11C11/4087 , G11C8/12
摘要： A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a capacitor. A word line multiple selection circuit is provided for selecting a plurality of the word lines. The multiple selection circuit simultaneously accesses all of the memory cells by selecting all the word lines of a memory array when a semiconductor memory is in a clear mode. In the clear mode a detector selects data lines of the memory array. A plate voltage control circuit controls a voltage at one plate of each of the capacitors in the memory cells. The plate control circuit changes a voltage at the plate to a preselected clear mode voltage when a semiconductor memory is in a clear mode. It is a feature of the invention that preselected data is written in the memory cells by data communication through the data lines during the clear mode. The preselected data includes at least one "1" data of the preselected data written in the memory cells. Subsequently to end the clear mode operation, the plate voltage control circuit changes the plate voltage for normal operations.
摘要翻译：一种具有多个字线的半导体存储器和与该字线相交的多条数据线。存储单元被布置在字线和数据线的节点处。每个存储单元都具有场效应晶体管和电容器。提供用于选择多个字线的字线多重选择电路。当半导体存储器处于清除模式时，多选择电路通过选择存储器阵列的所有字线来同时访问所有存储单元。在清除模式下，检测器选择存储器阵列的数据线。板电压控制电路控制存储单元中的每个电容器的一个板上的电压。当半导体存储器处于清除模式时，板控制电路将板处的电压改变为预选的清除模式电压。本发明的特征在于，在清除模式期间，通过数据线进行数据通信，将预选数据写入存储单元。预选数据包括写入存储单元的预选数据的至少一个“1”数据。随后结束清除模式操作，板电压控制电路改变正常操作的板电压。

53. 发明授权

US4716313A Pulse drive circuit 失效
标题翻译：脉冲驱动电路
公开(公告)号：US4716313A
公开(公告)日：1987-12-29
申请号：US058617
申请日：1987-06-03
申请人： Ryoichi Hori , Kiyoo Itoh , Jun Etoh
发明人： Ryoichi Hori , Kiyoo Itoh , Jun Etoh
IPC分类号： G11C11/419 , G11C11/401 , G11C11/409 , H03K19/017 , H03K19/0185 , H03K5/02 , H03K17/08 , H03K17/28 , H03K17/284
CPC分类号： H03K19/01707 , H03K19/018507
摘要： In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection.
摘要翻译：为了以高速度驱动电容负载而不会不期望地大大增加电路尺寸，提供驱动装置以根据有限的电压对电容负载充电。电压限制器耦合到提供预定有限电压的电源电压。耦合脉冲发生器以接收有限的电压并提供输出脉冲，其依次受限于电压限制器的输出电压的限制。驱动器耦合在电源电压和电容负载之间，并由脉冲发生器的输出脉冲控制。以这种方式，电容负载根据限制的电压通过驱动器充电。由于电压限制器不沿着驱动器和电容负载之间的串联连接布置，因此限压器的内部等效电阻不会有害地影响串联电阻。

54. 发明授权

US4675845A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4675845A
公开(公告)日：1987-06-23
申请号：US717490
申请日：1985-03-29
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G11C11/413 , G11C5/06 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/40
CPC分类号： G11C11/4096 , G11C11/4087 , G11C11/4097 , G11C5/06 , G11C5/063
摘要： A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.
摘要翻译：具有这样的结构的半导体存储器，其中与字线相交的每条数据线在其长度方向被分成多条子线，存储单元被布置在划分的子线和字线之间的相交点，公共输入/输出线路共同设置在多个这样的子线路上，公共输入/输出线路和多条子线路分别由开关元件连接，并且开关元件通过控制线路连接到解码器，并且通过控制被选择性地驱动从解码器产生的信号。

55. 发明授权

US4503522A Dynamic type semiconductor monolithic memory 失效
标题翻译：动态型半导体单片存储器
公开(公告)号：US4503522A
公开(公告)日：1985-03-05
申请号：US358678
申请日：1982-03-16
申请人： Jun Etoh , Yoshiki Kawajiri , Ryoichi Hori , Kiyoo Itoh
发明人： Jun Etoh , Yoshiki Kawajiri , Ryoichi Hori , Kiyoo Itoh
IPC分类号： G11C11/408 , G11C11/4096 , G11C7/00 , G11C11/40
CPC分类号： G11C11/4085 , G11C11/4096
摘要： A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory are each provided with a voltage compensating circuit for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit. Thus, the word line voltage is boosted twice.
摘要翻译：使用MOS晶体管的动态型半导体存储器，其中分别在字驱动器之前和之后的每个级提供利用电容的第一和第二升压电路。存储器的数据线各自设置有电压补偿电路，用于将用于将存储器单元充电的电压提高到高于用于在存储器单元中重写的源电压的电平。在产生字线驱动脉冲信号之后，第一升压电路被操作。随后，字驱动器选择晶体管截止，其后是第二升压电路的操作。因此，字线电压被提升两次。

56. 发明授权

US4475181A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4475181A
公开(公告)日：1984-10-02
申请号：US337099
申请日：1982-01-05
申请人： Jun Etoh , Ryoichi Hori , Yoshiki Kawajiri , Kiyoo Itoh
发明人： Jun Etoh , Ryoichi Hori , Yoshiki Kawajiri , Kiyoo Itoh
IPC分类号： G11C8/00 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/408 , G11C11/418 , H03K5/135 , G11C7/00
CPC分类号： H03K5/135 , G11C11/407 , G11C11/408 , G11C11/418 , G11C8/06 , G11C8/18
摘要： A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of memory cells. The semiconductor memory is equipped with address buffers exclusively for column and row addressing operations, respectively, the outputs of which are consecutively transmitted to column decoders and row decoders through common internal address lines.
摘要翻译：多路复用地址输入的半导体存储器用于通过公共外部地址线接收列地址和行地址，并且响应于第一和第二选通信号连续解码它们，从而选择一个存储单元。半导体存储器分别配备有用于列和行寻址操作的地址缓冲器，它们的输出通过公共内部地址线连续发送到列解码器和行解码器。

57. 发明授权

US08336528B2 EGR device 有权
标题翻译： EGR装置
公开(公告)号：US08336528B2
公开(公告)日：2012-12-25
申请号：US12309182
申请日：2007-06-28
申请人： Ryoichi Hori , Satoshi Kimura , Satoshi Tamagawa
发明人： Ryoichi Hori , Satoshi Kimura , Satoshi Tamagawa
IPC分类号： F02M25/07 , F02B47/08 , F02B33/44 , F02B29/04 , F01P1/06
CPC分类号： F02B29/0443 , F01P7/165 , F01P7/167 , F01P2003/182 , F01P2003/187 , F01P2007/168 , F01P2025/66 , F01P2060/02 , F02B29/0412 , F02M26/05 , F02M26/28 , Y02T10/146
摘要： An EGR device includes a first cooling passage that introduces a flowing medium discharged from an engine into a main radiator so that the flowing medium is cooled therein, and then returns the flowing medium to the engine, and a second cooling passage that introduces a part of the flowing medium cooled in the first cooling passage to a sub-radiator so that the flowing medium is further cooled therein. The second cooling passage introduces the flowing medium to an EGR cooler to return the flowing medium, which is discharged from the EGR cooler, to the engine.
摘要翻译： EGR装置包括：第一冷却通道，其将从发动机排出的流动介质引入主散热器，使流动介质冷却，然后将流动介质返回到发动机;以及第二冷却通道，流动介质在第一冷却通道中冷却到副散热器，使流动介质进一步冷却。第二冷却通道将流动介质引入EGR冷却器，以将从EGR冷却器排出的流动介质返回到发动机。

58. 发明申请

US20100001535A1 EXHAUST GAS THERMAL ENERGY RECOVERY SYSTEM OF HYBRID ELECTRIC VEHICLE 审中-公开
标题翻译：混合动力汽车排气热能恢复系统
公开(公告)号：US20100001535A1
公开(公告)日：2010-01-07
申请号：US12441082
申请日：2007-08-08
申请人： Satoshi Kimura , Ryoichi Hori , Shiro Nakajima , Norimitsu Matsudaira
发明人： Satoshi Kimura , Ryoichi Hori , Shiro Nakajima , Norimitsu Matsudaira
IPC分类号： H02K7/18 , F01N5/02
CPC分类号： F01N5/02 , B60K1/02 , B60K6/26 , B60L2270/44 , B60Y2400/206 , F01N3/043 , F01N3/2006 , F01N3/36 , F01N5/04 , F01N13/0093 , F01N2240/02 , F01N2260/08 , F01N2390/00 , F01N2410/00 , F01N2900/1621 , Y02A50/2322 , Y02T10/16 , Y02T10/26
摘要： An exhaust gas thermal energy recovery system of a hybrid electric vehicle includes a second catalytic converter 6, a cooling device 10, a resonance tube 8, control valves V1 and V2 and an electric generating device 9. After an engine 1 is stopped, the control valves V1 and V2 form a loop path 20, and the cooling device 10 cools down an exhaust gas downstream side of the second catalytic converter 6 so as to generate a temperature gradient.
摘要翻译：混合电动车辆的废气热能回收系统包括第二催化转化器6，冷却装置10，共振管8，控制阀V1和V2以及发电装置9.在发动机1停止之后，控制阀V1和V2形成环路20，并且冷却装置10冷却第二催化转化器6的排气下游侧，以产生温度梯度。

59. 发明授权

US07203101B2 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US07203101B2
公开(公告)日：2007-04-10
申请号：US11330220
申请日：2006-01-12
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C7/10
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括多个第一存储器阵列，多个第二存储器阵列，第一电压发生器和多个第一焊盘。半导体芯片被分成第一矩形区域，第二矩形区域和第三矩形区域，并且第三矩形区域布置在第一矩形区域和第二矩形区域之间。多个第一存储器阵列形成在第一矩形区域中。多个第二存储器阵列形成在第二矩形区域中。电压发生器和多个第一接合焊盘被布置在第三矩形区域中。多个第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和多个第二存储器阵列之间没有布置接合焊盘。

60. 发明申请

US20070051488A1 Heat exchanger for motor vehicle 审中-公开
标题翻译：机动车换热器
公开(公告)号：US20070051488A1
公开(公告)日：2007-03-08
申请号：US11505986
申请日：2006-08-18
申请人： Ryoichi Hori
发明人： Ryoichi Hori
IPC分类号： B60H1/00 , F28D1/04 , F28F9/02
CPC分类号： F28D1/0435 , F04D29/541 , F04D29/582 , F28F2215/02
摘要： A heat exchanger for a motor vehicle includes a pair of tanks apart from each other, and a core part including a plurality of tubes and a plurality of fins. Each of the fins is arranged between the adjacent tubes, and the tubes are fixed at both end portions thereof with the tanks so that circulating medium can be cooled by air flow running through the core part and flows through the tubes and tanks. Connecting portions of the tubes and the tanks are covered by a windbreak member so that the connecting portions are prevented from being hit by the air flow running through the core port.
摘要翻译：一种用于机动车辆的热交换器包括彼此分开的一对罐，以及包括多个管和多个翅片的芯部。每个翅片布置在相邻的管之间，并且管的两端部与罐固定，使得可以通过流过芯部的气流来冷却循环介质并流过管和罐。管和罐的连接部分被防风构件覆盖，使得防止连接部分被流经核心端口的气流撞击。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式