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    • 52. 发明申请
    • USING CAMERA SIGNATURES FROM UPLOADED IMAGES TO AUTHENTICATE USERS OF AN ONLINE SYSTEM
    • 使用上传图像中的相机签名来确认在线系统的用户
    • US20120070029A1
    • 2012-03-22
    • US12884137
    • 2010-09-16
    • Daniel Gregory MurielloStephen Charles HeiseJie Chen
    • Daniel Gregory MurielloStephen Charles HeiseJie Chen
    • G06K9/00
    • G06F21/44
    • Users of an online system are authenticated based on signatures of cameras that were used to capture images uploaded to the online system. Users of an online system upload photos taken from their cameras. The online system extracts characteristic information about the camera that captured the photos. This information includes a mapping of faulty pixels, metadata included with the photos, a naming convention, and the like. The online system stores an association between the user and the camera. This association is used for authentication of the user. For authentication, the user is asked to upload new photos taken from the camera that the user used previously. The information extracted from the newly uploaded photos is matched against stored information of cameras used previously by the user. The user is successfully authenticated if the camera used for the newly uploaded photos matches a previously stored camera.
    • 在线系统的用户基于用于捕获上传到在线系统的图像的相机的签名进行身份验证。 在线系统的用户上传从相机拍摄的照片。 在线系统提取拍摄照片的相机的特征信息。 该信息包括错误像素的映射,照片附带的元数据,命名约定等。 在线系统存储用户和相机之间的关联。 该关联用于用户的认证。 对于认证,用户被要求上传用户以前使用的相机拍摄的新照片。 从新上传的照片提取的信息与用户先前使用的相机的存储信息相匹配。 如果用于新上传的照片的相机与先前存储的相机匹配,则用户已成功验证。
    • 53. 发明授权
    • Reduced power output buffer
    • 减少功率输出缓冲器
    • US08138785B2
    • 2012-03-20
    • US12586288
    • 2009-09-18
    • Jie ChenTing-Yen ChiangKuang-Yu ChenChen Yu WangJoe Froniewski
    • Jie ChenTing-Yen ChiangKuang-Yu ChenChen Yu WangJoe Froniewski
    • H03K19/0175
    • H03K19/018521
    • A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.
    • 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路,该时钟发生电路耦合到用于PC的输出缓冲器,该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸,将电压节点的阻抗与负载阻抗之一相匹配。
    • 56. 发明申请
    • System for fext cancellation of multi-channel transceivers with precoding
    • 用于预编码的多通道收发器的消除系统
    • US20110261865A1
    • 2011-10-27
    • US12806556
    • 2010-08-16
    • Jie ChenKeshab K. Parhi
    • Jie ChenKeshab K. Parhi
    • H04B15/00H04L27/01H04B1/38
    • H04L25/03343H04L25/03057
    • The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a novel approach is proposed to deal with FEXT interferences in the application of high/ultra-high speed Ethernet systems. Compared with the traditional FEXT cancellation approaches, the proposed FEXT canceller can deal with the non-causal part of FEXT, and thus can achieve better cancellation performance. Instead of using the conventional DFE, structure, TH precoding technique is incorporated into the proposed design to alleviate the error propagation problem. The resulting FEXT cancellers do not contain feedback loops which makes the high speed VLSI implementation easy. A modified design is also developed by using a finite signal as the input to the FEXT canceller such that the hardware complexity of the proposed FEXT canceller can be reduced.
    • 本发明涉及多通道数据传输系统中的数据处理技术。 在本发明中,提出了一种新颖的方法来处理高/超高速以太网系统的应用中的FEXT干扰。 与传统的FEXT取消方法相比,提出的FEXT消除器可以处理FEXT的非因果部分,从而可以实现更好的取消性能。 代替使用常规的DFE,结构,TH预编码技术被并入所提出的设计中以减轻误差传播问题。 所产生的FEXT消除器不包含使得高速VLSI实现变得容易的反馈回路。 还通过使用有限信号作为FEXT消除器的输入来开发修改的设计,使得可以减少所提出的FEXT消除器的硬件复杂性。
    • 58. 发明申请
    • NEW PROCESS FOR RESOLVING S-3- (AMINOMETHYL)-5-METHYLHEXANOIC ACID
    • 用于分解S-3-(氨基甲酰基)-5-甲基六氢叶酸的新方法
    • US20110098502A1
    • 2011-04-28
    • US12811418
    • 2008-01-01
    • Jiankang XuDa ZhangMeiqi YeJie ChenYongbing GuoYongjiang Hu
    • Jiankang XuDa ZhangMeiqi YeJie ChenYongbing GuoYongjiang Hu
    • C07C227/36
    • C07C227/34C07C229/08
    • The present invention relates to a process for resolving S-3-(Aminomethyl)-5-methylhexanoic acid, which adopts benzoyl-L-glutamic acid, 4-methyl benzoyl-L-glutamic acid, benzene sulfonyl-L-glutamic acid or 4-methyl benzene sulfonyl-L-glutamic acid as a resolution agent to make a first resolution to racemic 3-aminomethyl-5-methylhexanoic acid, and adopts the resolution agent same to that of the first resolution to make a second resolution to the first resolution product to obtain the second resolution product, thus the resolution salt product is obtained, and further hydrolyzed by an acid, the resolution agent is extracted to be separated, the pH is adjusted to be neutral, the product S-3-(Aminomethyl)-5-methylhexanoic acid, i.e. the pregabalin, is then precipitated by distillation, therefore the present invention has the characteristics of polluting the environment slightly, high efficiency and stability, simpleness and practicality, producing product with high purity and a low sproduction cost, and is suitable for large-scale production.
    • 本发明涉及一种分离S-3-(氨基甲基)-5-甲基己酸的方法,该方法采用苯甲酰基-L-谷氨酸,4-甲基苯甲酰基-L-谷氨酸,苯磺酰基-L-谷氨酸或4 甲基苯磺酰基-L-谷氨酸作为拆分剂,首先拆分为外消旋的3-氨基甲基-5-甲基己酸,并采用与第一分辨率相同的分解剂,以第一分辨率作第二分辨率 得到第二分解产物,得到分解盐产物,并进一步用酸水解,提取分离剂分离,将pH调节为中性,产物S-3-(氨基甲基) - 然后通过蒸馏沉淀5-甲基己酸,即普瑞巴林,因此本发明具有轻微,高效和稳定,简单和实用的污染环境的特点,生产高纯度和低产量的产品 成本高,适合大规模生产。
    • 59. 发明申请
    • System for low complexity adaptive ECHO and NEXT cancellers
    • 低复杂度自适应ECHO和NEXT消除器的系统
    • US20110044448A1
    • 2011-02-24
    • US12806539
    • 2010-08-16
    • Jie ChenKeshab K. Parhi
    • Jie ChenKeshab K. Parhi
    • H04M9/08
    • H04B3/23
    • The present invention relates to design and implementation of low complexity adaptive echo and NEXT cancellers in multi-channel data transmission systems. In this invention, a highly efficient weight update scheme is proposed to reduce the computational cost of the weight update part in adaptive echo and NEXT cancellers. Based on the proposed scheme, the hardware complexity of the weight update part can be further reduced by applying the word-length reduction technique. The proposed scheme is general and suitable for real applications such as design of a low complexity transceiver in 10GBase-T. Different with prior work, this invention considers the complexity reduction in weight update part of the adaptive filters such that the overall complexity of these adaptive cancellers can be significantly reduced.
    • 本发明涉及多通道数据传输系统中低复杂度自适应回波和NEXT消除器的设计和实现。 在本发明中,提出了一种高效的加权更新方案,以减少自适应回波和NEXT消除器中权重更新部分的计算成本。 基于所提出的方案,可以通过应用字长缩减技术来进一步降低权重更新部分的硬件复杂度。 所提出的方案是一般的,适用于实际应用,例如在10GBase-T中设计低复杂度收发器。 与现有技术不同,本发明考虑了自适应滤波器的权重更新部分的复杂度降低,使得这些自适应消除器的整体复杂度可以显着降低。
    • 60. 发明申请
    • Reduced power output buffer
    • 减少功率输出缓冲器
    • US20100148817A1
    • 2010-06-17
    • US12586288
    • 2009-09-18
    • Jie ChenTing-Yen ChiangKuang-Yu ChenChen Yu WangJoe Froniewski
    • Jie ChenTing-Yen ChiangKuang-Yu ChenChen Yu WangJoe Froniewski
    • H03K19/003H03K19/094
    • H03K19/018521
    • A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.
    • 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路,该时钟发生电路耦合到用于PC的输出缓冲器,该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸,将电压节点的阻抗与负载阻抗之一相匹配。