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51. 发明授权

US08275963B2 Asynchronous memory move across physical nodes with dual-sided communication 有权
标题翻译：异步存储器通过双面通信跨物理节点移动
公开(公告)号：US08275963B2
公开(公告)日：2012-09-25
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

52. 发明授权

US07958327B2 Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture 有权
标题翻译：通过在指令集体系结构中执行AMM存储指令来执行异步存储器移动（AMM）
公开(公告)号：US07958327B2
公开(公告)日：2011-06-07
申请号：US12024494
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM ST instruction moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location. When the move is completed in the virtual address space, the AMM operation performs the physical move of the data to the second memory location outside the processor core, without processor involvement.
摘要翻译：具有处理器和存储器的数据处理系统包括提供异步存储器移动（AMM）存储（ST）指令的指令集架构（ISA）。当处理器执行AMM ST指令时，处理器执行一系列功能，其启动异步存储器移动（AMM）操作。 AMM ST指令通过以下方式将数据从具有第一实际地址的第一存储器位置移动到具有第二实际地址的第二存储器位置：（a）使用存储器映射的源有效地址来执行虚拟地址空间中的数据移动到第一存储器位置和存储器映射到第二存储器位置的目的地有效地址。当在虚拟地址空间中完成移动时，AMM操作将数据物理移动到处理器核心外部的第二存储器位置，而无需处理器参与。

53. 发明授权

US07941627B2 Specialized memory move barrier operations 失效
标题翻译：专业记忆移动屏障操作
公开(公告)号：US07941627B2
公开(公告)日：2011-05-10
申请号：US12024674
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译：指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。

54. 发明申请

US20090199200A1 Mechanisms to Order Global Shared Memory Operations 有权
标题翻译：订购全局共享内存操作的机制
公开(公告)号：US20090199200A1
公开(公告)日：2009-08-06
申请号：US12024367
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F9/50
CPC分类号： G06F12/0284 , G06F12/109 , G06F2212/656
摘要： A method and data processing system for performing fence operations within a global shared memory (GSM) environment having a local task executing on a processor and providing GSM commands for processing by a host fabric interface (HFI) window that is allocated to the task. The HFI window has one or more registers for use during local fence operations. A first register tracks a first count of task-issued GSM commands, and a second register tracks a second count of GSM operations being processed by the HFI. The processing logic detects a locally-issued fence operation, and responds by performing a series of operations, including: automatically stopping the task from issuing additional GSM commands; monitoring for completion of all the task-issued GSM commands at the HFI; and triggering a resumption of issuance of GSM commands by the task when the completion of all previous task-issued GSM commands is registered by the HFI.
摘要翻译：一种用于在全局共享存储器（GSM）环境内执行栅栏操作的方法和数据处理系统，其具有在处理器上执行的本地任务并提供用于由分配给该任务的主机结构接口（HFI）窗口进行处理的GSM命令。 HFI窗口有一个或多个寄存器用于本地栅栏操作。第一寄存器跟踪任务发出的GSM命令的第一计数，第二寄存器跟踪由HFI正在处理的GSM操作的第二计数。处理逻辑检测本地发出的围栏操作，并通过执行一系列操作进行响应，包括：自动停止任务发出附加的GSM命令; 监测在HFI完成所有任务发布的GSM命令; 并且当HFI注册所有先前任务发出的GSM命令的完成时，通过任务触发恢复发出GSM命令。

55. 发明申请

US20090198955A1 ASYNCHRONOUS MEMORY MOVE ACROSS PHYSICAL NODES (DUAL-SIDED COMMUNICATION FOR MEMORY MOVE) 有权
标题翻译：异常记忆移动物理名称（双面通信用于记忆移动）
公开(公告)号：US20090198955A1
公开(公告)日：2009-08-06
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

56. 发明申请

US20090198934A1 FULLY ASYNCHRONOUS MEMORY MOVER 失效
标题翻译：充分的异常记忆运动
公开(公告)号：US20090198934A1
公开(公告)日：2009-08-06
申请号：US12024613
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02 , G06F12/14 , G06F9/46
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation.
摘要翻译：数据处理系统具有耦合到处理器的处理器和存储器以及耦合到处理器的异步存储器移动器。异步存储器移动器具有用于从处理器接收一组参数的寄存器，这些参数与虚拟地址空间中由处理器发起的异步存储器移动（AMM）操作相关联，利用源有效地址和目的地有效地址。异步存储器移动器执行AMM操作以将来自具有与源有效地址相对应的源实际地址的第一物理存储器位置的数据移动到具有与目的地有效地址相对应的目的地实际地址的第二物理存储器位置。异步存储器移动器具有相关的片外转换机制。因此，AMM操作独立于处理器，并且处理器继续处理独立于AMM操作的其他操作。

57. 发明申请

US20090198917A1 SPECIALIZED MEMORY MOVE BARRIER OPERATIONS 失效
标题翻译：专用记忆移动障碍操作
公开(公告)号：US20090198917A1
公开(公告)日：2009-08-06
申请号：US12024674
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译：指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。

58. 发明申请

US20090198897A1 CACHE MANAGEMENT DURING ASYNCHRONOUS MEMORY MOVE OPERATIONS 有权
标题翻译：非正常记忆移动操作期间的缓存管理
公开(公告)号：US20090198897A1
公开(公告)日：2009-08-06
申请号：US12024526
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3877 , G06F12/10
摘要： A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
摘要翻译：数据处理系统包括用于完成异步存储器移动（AMM）操作的机制，其中处理器接收AMM ST指令并处理虚拟地址空间中的数据的处理器级移动，然后异步存储器移动器完成物理移动实际地址空间（内存）中的数据。 AMM ST指令的状态/控制字段在完成AMM操作时包括对低级缓存的请求处理的指示。当状态/控制字段指示应该执行至少一个缓存的更新时，异步存储器移动器自动将数据的副本从数据移动转发到较低级的高速缓存，并触发高速缓存的一致性状态的更新其中放置数据副本的行。

59. 发明申请

US20090198762A1 Mechanism to Provide Reliability Through Packet Drop Detection 失效
标题翻译：通过丢包检测提供可靠性的机制
公开(公告)号：US20090198762A1
公开(公告)日：2009-08-06
申请号：US12024600
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F9/544
摘要： A method and a data processing system for completing checkpoint processing of a distributed job with local tasks communicating with other remote tasks via a host fabric interface (HFI) and assigned HFI window. Each HFI window has a send count and a receive count, which tracks GSM messages that are sent from and received at the HFI window. When a checkpoint is initiated by a master task, each local task forwards the send count and the receive count to the master task. The master task sums the respective counts and then compares the totals to each other. When the send count total is equal to the receive count total, the tasks are permitted to continue processing. However, when the send count total is not equal to the receive count total, the master task notifies each task of the job to rollback to a previous checkpoint or kill the job execution.
摘要翻译：一种方法和数据处理系统，用于通过主机结构接口（HFI）和分配的HFI窗口完成与其他远程任务通信的本地任务的分布式作业的检查点处理。每个HFI窗口都有发送计数和接收计数，用于跟踪在HFI窗口发送和接收的GSM消息。当主任务启动检查点时，每个本地任务将发送计数和接收计数转发给主任务。主任务对各个计数进行相加，然后将总计相互比较。当发送计数总数等于接收计数总数时，允许任务继续处理。但是，当发送计数总数不等于接收计数总数时，主任务会通知作业的每个任务以回滚到先前的检查点或终止作业执行。

60. 发明授权

US07379444B2 Method to recover from node failure/recovery incidents in distributed systems in which notification does not occur 失效
标题翻译：在不发生通知的分布式系统中从节点故障/恢复事件中恢复的方法
公开(公告)号：US07379444B2
公开(公告)日：2008-05-27
申请号：US10351823
申请日：2003-01-27
申请人： Robert S. Blackmore , Amy X. Chen , Scott D. Epter , Chulho Kim , Rajeev Sivaram
发明人： Robert S. Blackmore , Amy X. Chen , Scott D. Epter , Chulho Kim , Rajeev Sivaram
IPC分类号： H04L1/12 , H04L12/26
CPC分类号： H04L29/06 , H04L67/10 , H04L69/329 , H04L69/40
摘要： Epoch numbers are maintained in a pair wise fashion at a plurality of communication endpoints to provide communication consistency and recovery from a range of failure conditions including total or partial node failure and subsequent recovery. Once an epoch state inconsistency is recognized, negotiation procedures provide an effective mechanism to reestablish valid communication links without the need to employ global variables which inherently possess greater transmission and overhead requirements needed to maintain communications. Renegotiation of recognizably valid epoch numbers occurs on a pair wise basis.
摘要翻译：在多个通信端点以成对方式保持时代号，以从包括全部或部分节点故障和随后恢复的一系列故障条件提供通信一致性和恢复。一旦识别出时代状态不一致，谈判程序就提供了有效的机制来重新建立有效的通信链路，而不需要使用固有地拥有维持通信所需的更大的传输和开销要求的全局变量。可识别的有效时代数的重新协商是以双重依据为基础进行的。

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