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51. 发明授权

US07736830B2 Method for forming circuit pattern 失效
标题翻译：电路图案形成方法
公开(公告)号：US07736830B2
公开(公告)日：2010-06-15
申请号：US12198540
申请日：2008-08-26
申请人： Akihiko Kamada , Norio Sakai , Issei Yamamoto
发明人： Akihiko Kamada , Norio Sakai , Issei Yamamoto
IPC分类号： G03G13/20
CPC分类号： H05K1/167 , G03G9/081 , G03G9/0823 , G03G9/0833 , G03G9/08711 , G03G9/09725 , G03G9/0975 , G03G13/00 , G03G13/013 , G03G15/224 , G03G15/225 , G03G15/6585 , H05K1/0306 , H05K1/092 , H05K3/102 , H05K3/1266 , H05K3/207 , H05K2203/0143 , H05K2203/0517
摘要： A method for forming circuit patterns having different resistances. The method includes (1) a first step of forming a first toner image using a first toner and a second toner image using a second toner, each by electrophotography, the first toner containing a resistive material, the second toner having a resistance different from that of the first toner; and (2) a second step of transferring and fixing the first toner image and the second toner image to an object to be printed such as a ceramic green sheet, to form a circuit pattern.
摘要翻译：一种用于形成具有不同电阻的电路图案的方法。该方法包括：（1）第一步骤，通过电子照相法使用第一调色剂和第二调色剂形成第一调色剂图像，第一调色剂图像使用第二调色剂，第一调色剂含有电阻材料，第二调色剂的电阻不同于的第一个墨粉; 和（2）将第一调色剂图像和第二调色剂图像转印并固定到诸如陶瓷生片的待印刷对象上的第二步骤，以形成电路图案。

52. 发明授权

US07569925B2 Module with built-in component 有权
标题翻译：具有内置组件的模块
公开(公告)号：US07569925B2
公开(公告)日：2009-08-04
申请号：US11462395
申请日：2006-08-04
申请人： Yoshihiko Nishizawa , Norio Sakai
发明人： Yoshihiko Nishizawa , Norio Sakai
IPC分类号： H01L23/053 , H01L23/12 , H01L23/06 , H01L23/29
CPC分类号： H01L23/24 , H01L23/13 , H01L23/5384 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15153 , H01L2924/1517 , H01L2924/1532 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3025 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A module with a built-in component is produced by disposing a cavity on a mounting surface side of a ceramic multilayer substrate, storing a circuit component therein and, thereafter, performing resin molding. A second resin portion is disposed on the mounting surface side of the ceramic multilayer substrate so as to continuously cover a frame-shaped portion and a first resin portion molded. External terminal electrodes are disposed on an outer surface of the second resin portion.
摘要翻译：具有内置部件的模块通过在陶瓷多层基板的安装表面侧设置空腔，在其中存储电路部件，然后进行树脂成型而制造。第二树脂部分设置在陶瓷多层基板的安装表面侧，以连续地覆盖框状部分和模制的第一树脂部分。外部端子电极设置在第二树脂部分的外表面上。

53. 发明申请

US20080305425A1 METHOD FOR FORMING CIRCUIT PATTERN 失效
标题翻译：形成电路图的方法
公开(公告)号：US20080305425A1
公开(公告)日：2008-12-11
申请号：US12198540
申请日：2008-08-26
申请人： Akihiko Kamada , Norio Sakai , Issei Yamamoto
发明人： Akihiko Kamada , Norio Sakai , Issei Yamamoto
IPC分类号： G03G13/20
CPC分类号： H05K1/167 , G03G9/081 , G03G9/0823 , G03G9/0833 , G03G9/08711 , G03G9/09725 , G03G9/0975 , G03G13/00 , G03G13/013 , G03G15/224 , G03G15/225 , G03G15/6585 , H05K1/0306 , H05K1/092 , H05K3/102 , H05K3/1266 , H05K3/207 , H05K2203/0143 , H05K2203/0517
摘要： A method for forming circuit patterns having different resistances. The method includes (1) a first step of forming a first toner image using a first toner and a second toner image using a second toner, each by electrophotography, the first toner containing a resistive material, the second toner having a resistance different from that of the first toner; and (2) a second step of transferring and fixing the first toner image and the second toner image to an object to be printed such as a ceramic green sheet, to form a circuit pattern.
摘要翻译：一种用于形成具有不同电阻的电路图案的方法。该方法包括：（1）第一步骤，通过电子照相法使用第一调色剂和第二调色剂形成第一调色剂图像，第一调色剂图像使用第二调色剂，第一调色剂含有电阻材料，第二调色剂的电阻不同于的第一个墨粉; 和（2）将第一调色剂图像和第二调色剂图像转印并固定到诸如陶瓷生片的待印刷对象上的第二步骤，以形成电路图案。

54. 发明授权

US07450395B2 Circuit module and circuit device including circuit module 有权
标题翻译：电路模块和电路设备包括电路模块
公开(公告)号：US07450395B2
公开(公告)日：2008-11-11
申请号：US12100479
申请日：2008-04-10
申请人： Norio Sakai
发明人： Norio Sakai
IPC分类号： H05K7/00
CPC分类号： H01L25/165 , H01L23/24 , H01L23/49822 , H01L23/49833 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/09701 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H05K1/0306 , H05K1/141 , H05K3/284 , H05K3/3442 , H05K3/4611 , H05K3/4629 , H05K2201/09427 , H05K2201/10378 , H05K2201/2018 , H05K2203/1572 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A circuit module includes connection electrodes on a plate-shaped board and connection electrodes on a frame-shaped board that are bonded together with conductive bonding materials there between. Circuit components are provided in portions of a surface of the plate-shaped board, the portions being located inward relative to the frame-shaped board. A sealing resin is filled and cured in a cavity, which is defined by the frame-shaped board and the plate-shaped board. Since the center of each of the connection electrodes on the frame-shaped board is inwardly displaced relative to the center of a corresponding one of the connection electrodes on the plate-shaped board by α, a curing contraction stress of the sealing resin is mitigated by a curing contraction stress of the conductive bonding materials. Thus, deformation of the frame-shaped board is suppressed.
摘要翻译：电路模块包括板状板上的连接电极和框架形板上的连接电极，其间连接有导电接合材料。电路部件设置在板状板的表面的一部分中，该部分相对于框状板位于内侧。密封树脂在由框状板和板状板限定的空腔中填充和固化。由于框架板上的每个连接电极的中心相对于板状板上相应的一个连接电极的中心向内移位，所以密封树脂的固化收缩应力被减轻导电接合材料的固化收缩应力。因此，能够抑制框状板的变形。

55. 发明授权

US5635670A Multilayer electronic component 失效
标题翻译：多层电子元件
公开(公告)号：US5635670A
公开(公告)日：1997-06-03
申请号：US589534
申请日：1996-01-05
申请人： Kenji Kubota , Norio Sakai , Shoichi Kawabata
发明人： Kenji Kubota , Norio Sakai , Shoichi Kawabata
IPC分类号： H01G2/06 , H01G4/232 , H01L21/66 , H01L23/10 , H01L23/498 , H01L23/58 , H05K1/03 , H05K1/09 , H05K3/00 , H05K3/34 , H05K3/40 , H02G3/08 , H01L23/02 , H01R29/00 , H05K7/00
CPC分类号： H01G4/232 , H01G2/065 , H01L22/20 , H01L22/32 , H01L23/10 , H01L23/49805 , H05K3/403 , H01L2924/014 , H01L2924/16152 , H05K1/0306 , H05K1/092 , H05K2201/09181 , H05K2201/09563 , H05K2201/09845 , H05K3/0052 , H05K3/3442 , H05K3/4061 , Y10T29/435 , Y10T29/49004 , Y10T29/4902 , Y10T29/49165 , Y10T29/49169
摘要： In order to provide a multilayer electronic component which can reduce arrangement pitches for external electrodes, via holes filled up with conductive materials are provided in a mother laminate, which is obtained by stacking a plurality of insulating sheets with interposition of conductor films, in positions parted by cutting. The conductive materials define external electrodes of individual multilayer electronic components which are obtained by cutting the mother laminate. No specific step is required for forming the external electrodes, and characteristics of each multilayer electronic component can be efficiently measured in the state of the mother laminate.
摘要翻译：为了提供一种可以减少外部电极的布置间距的多层电子部件，在母层叠体中设置填充有导电材料的通孔，该母层叠体通过在分开的位置层叠多个绝缘片而插入导体膜而获得通过切割。导电材料限定通过切割母层压板而获得的各个多层电子部件的外部电极。不需要形成外部电极的特定步骤，并且可以在母体层叠体的状态下有效地测量每个多层电子部件的特性。

56. 发明授权

US5435875A Method of manufacturing cavitied ceramic multilayer block 失效
标题翻译：空心陶瓷多层块的制造方法
公开(公告)号：US5435875A
公开(公告)日：1995-07-25
申请号：US186423
申请日：1994-01-25
申请人： Tsuyoshi Saitoh , Shoichi Kawabata , Norio Sakai
发明人： Tsuyoshi Saitoh , Shoichi Kawabata , Norio Sakai
IPC分类号： B28B3/02 , B32B18/00 , H01L21/48 , H01L23/057 , H01L23/12 , H05K3/46 , B29C31/04 , B32B31/04 , B32B31/20
CPC分类号： B32B38/1841 , B32B18/00 , B32B37/0023 , B32B37/10 , B32B37/26 , H01L21/4807 , H01L21/4857 , H01L23/057 , B32B2315/02 , B32B2457/08 , C04B2237/32 , C04B2237/62 , C04B2237/704 , H01L2924/0002
摘要： When a plurality of ceramic green sheets provided with cavity holes are respectively pressed by an elastic member, rigid plates which are sized to be in contact with overall major surfaces of the respective ceramic green sheets and provided with holes equivalent to or slightly smaller than the cavity holes are interposed between the elastic member and the respective ceramic green sheets. Thus, the cavity holes are inhibited from undesired deformation caused by deformation of the elastic member.
摘要翻译：当设置有空腔孔的多个陶瓷生坯分别被弹性部件按压时，刚性板的尺寸设计成与各个陶瓷生坯的整个主表面接触并且设置有等于或略小于腔的孔在弹性构件和各个陶瓷生片之间插入孔。因此，可以防止空腔孔被弹性构件的变形引起的不期望的变形。

57. 发明授权

US5274916A Method of manufacturing ceramic multilayer electronic component 失效
标题翻译：制造陶瓷多层电子元件的方法
公开(公告)号：US5274916A
公开(公告)日：1994-01-04
申请号：US992161
申请日：1992-12-17
申请人： Shoichi Kawabata , Norio Sakai , Kenji Minowa
发明人： Shoichi Kawabata , Norio Sakai , Kenji Minowa
IPC分类号： H01F27/00 , H01G4/12 , H01L21/48 , H01L23/12 , H05K1/03 , H05K1/09 , H05K3/40 , H05K3/46 , B44C1/22
CPC分类号： H05K3/4061 , H01L21/481 , H01L21/486 , H05K1/0306 , H05K1/092 , H05K2203/0156 , H05K2203/0191 , H05K2203/066 , H05K2203/082 , H05K3/4611 , H05K3/4629 , Y10T29/49158 , Y10T29/49165
摘要： A ceramic green sheet is formed on a carrier film; both the ceramic green sheet and the carrier film are cut into prescribed dimensions; a hole to serve as a via hole is provided in the ceramic green sheet while the ceramic green sheet is maintained in the state backed with the carrier film; the hole is filled up with a conductive paste while the ceramic green sheet is in this state; an interconnection pattern is formed on the ceramic green sheet which is still backed up with the carrier film; and the ceramic green sheet is then separated from the carrier film and is then immediately stacked in order on other ceramic green sheets. Thus, it is possible to improve the accuracy in stacking of ceramic green sheets in a method of manufacturing a ceramic multilayer circuit board having portions electrically connected through via holes.
摘要翻译：在载体膜上形成陶瓷生片; 将陶瓷生片和载体膜切割成规定尺寸; 在陶瓷生片中设置用作通孔的孔，同时陶瓷生片保持在载体膜的状态下; 当陶瓷生坯处于该状态时，用导电膏填充孔; 在陶瓷生片上形成有与载体膜相配合的互连图案; 然后将陶瓷生片与载体膜分离，然后依次堆叠在其它陶瓷生片上。因此，在具有通过通孔电连接的部分的陶瓷多层电路板的制造方法中，可以提高陶瓷生片的层叠精度。

58. 发明授权

US5261986A Method of fabricating ceramic laminated electronic component 失效
标题翻译：制造陶瓷层压电子元器件的方法
公开(公告)号：US5261986A
公开(公告)日：1993-11-16
申请号：US799043
申请日：1991-11-26
申请人： Shoichi Kawabata , Hiromichi Wakatsuki , Norio Sakai , Keiichi Okada
发明人： Shoichi Kawabata , Hiromichi Wakatsuki , Norio Sakai , Keiichi Okada
IPC分类号： H01G4/12 , B28B3/02 , B28B11/00 , B28B13/04 , H01G4/30 , H01G4/40 , H05K1/02 , H05K1/03 , H05K1/09 , H05K3/46 , C04B37/00
CPC分类号： H05K3/4629 , B28B11/003 , B28B13/04 , B28B3/024 , H01G4/308 , H01G4/40 , H05K3/4638 , H05K1/0269 , H05K1/0306 , H05K1/092 , H05K2201/09781 , H05K2203/166 , Y10T156/1093
摘要： A method of fabricating a ceramic laminated electronic component including the steps of preparing a plurality of ceramic green sheets each having electrode pastes in a plurality of regions and having positioning marks printed in positions having a constant positional relationship to the electrode pastes, removing wrinkles in each of the ceramic green sheets to flatten the ceramic green sheet on a suction plate, and transferring the flattened ceramic green sheet to a laminating stage by a suction chuck, laminating the ceramic green sheet on the laminating stage on the basis of the above positioning marks, and preliminarily fixing the ceramic green sheets to each other in the case of the lamination in obtaining a mother ceramic laminated body for the ceramic laminated electronic component.
摘要翻译：一种制造陶瓷层压电子部件的方法，包括以下步骤：在多个区域中制备多个具有电极浆料的陶瓷生片，并将定位标记印刷在与电极浆料具有恒定位置关系的位置，从而去除每个的陶瓷生片将吸附板上的陶瓷生片平坦化，并通过吸盘将平坦化的陶瓷生片转移到层压台，基于上述定位标记将陶瓷生片层压在层压台上，并且在层叠的情况下，预先将陶瓷生片彼此固定，以获得用于陶瓷层叠电子部件的母陶瓷层叠体。

59. 发明授权

US4848106A Compression membrane 失效
标题翻译：压膜
公开(公告)号：US4848106A
公开(公告)日：1989-07-18
申请号：US158240
申请日：1988-02-19
申请人： Shoichi Hayashi , Norio Sakai , Hidetoshi Ishihara
发明人： Shoichi Hayashi , Norio Sakai , Hidetoshi Ishihara
IPC分类号： B30B9/22 , D06F47/06
CPC分类号： D06F47/06 , B30B9/22
摘要： The invention resides in a compression membrane for wringing liquid out of an object to be compressed, characterized in that its marginal portion whose width is of the order of 15%-35% of the width in the radial direction of the membrane body is made smaller in stretchability than the other portion, whereby no tear of the object to be compressed does not tear during the dehydration thereof.
摘要翻译：本发明涉及一种用于将液体从待压缩物体中拧出的压缩膜，其特征在于，其宽度为膜体径向宽度的15％-35％的边缘部分变小在拉伸性方面比其他部分的拉伸性好，因此在其脱水过程中，被压缩物体的撕裂不会撕裂。

60. 发明授权

US4766412A Electronic composite component having resistor element 失效
标题翻译：具有电阻元件的电子复合元件
公开(公告)号：US4766412A
公开(公告)日：1988-08-23
申请号：US52490
申请日：1987-05-20
申请人： Shin-ichi Takakura , Shigehiro Nojiri , Norio Sakai
发明人： Shin-ichi Takakura , Shigehiro Nojiri , Norio Sakai
IPC分类号： H01C13/00 , H01F27/00 , H01G4/40 , H03H1/02
CPC分类号： H01G4/40
摘要： An electronic composite component is composed of a resistor element formed by a resistor film and a functional element such as a capacitor element which is electrically connected in parallel with the resistor element. The functional element has a body and a pair of terminal electrodes formed on respective end surfaces of the body. A serially extending electric insulation layer is formed on the surface of the body to partially cover the pair of terminal electrodes. This electric insulation layer is formed to selectively determine the distance between exposed regions of the terminal electrodes. The resistor film forming the resistor element is provided to partially cover and interconnect the exposed regions of the terminal electrodes and cross the boundary lines between the insulation layer and the exposed regions of the terminal electrodes, to electrically connect the pair of terminal electrodes with each other, through a resistance selectively determined according to the distance between the exposed regions of the terminal electrodes.
摘要翻译：电子复合元件由电阻膜形成的电阻元件和与电阻元件并联电连接的电容器元件等功能元件构成。功能元件具有形成在主体的相应端表面上的主体和一对端子电极。在主体的表面上形成一个串联延伸的电绝缘层，以部分地覆盖该对端子电极。形成电绝缘层以选择性地确定端子电极的暴露区域之间的距离。形成电阻元件的电阻膜被设置成部分地覆盖和互连端电极的暴露区域并与绝缘层和端子电极的暴露区域之间的边界线交叉，以将该对端子电极彼此电连接通过根据端子电极的暴露区域之间的距离选择性地确定的电阻。

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