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51. 发明授权

US06356118B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06356118B1
公开(公告)日：2002-03-12
申请号：US09549711
申请日：2000-04-14
申请人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
发明人： Kunihito Rikino , Yasuhiko Sasaki , Kazuo Yano , Naoki Kato
IPC分类号： H03K19094
CPC分类号： H01L27/092 , H01L27/0203 , H03K19/1737
摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
摘要翻译：通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。这可以使紧凑，快速的电路。

52. 发明授权

US06313666B1 Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit 有权
标题翻译：包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法
公开(公告)号：US06313666B1
公开(公告)日：2001-11-06
申请号：US09331780
申请日：1999-06-24
申请人： Shunzo Yamashita , Kazuo Yano
发明人： Shunzo Yamashita , Kazuo Yano
IPC分类号： H03K19094
CPC分类号： H03K19/1736 , G06F17/505 , H03K19/1737
摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).
摘要翻译：为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射成为2-inut，1输出，1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门如果通过替换获得的预定电路特性的值更接近于最佳值（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通路小，则逻辑上等效于通过转换器选择器的NAND或NOR逻辑）晶体管逻辑电路）。

53. 发明授权

US06291852B1 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US06291852B1
公开(公告)日：2001-09-18
申请号：US09521970
申请日：2000-03-09
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.
摘要翻译：一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。根据一个实施例，提供了从沟道隔离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。

54. 发明授权

US5923189A Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections 失效
标题翻译：半导体集成电路由具有不同相互连接的通过晶体管电路组成
公开(公告)号：US5923189A
公开(公告)日：1999-07-13
申请号：US633053
申请日：1996-04-16
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： G06F17/50 , H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736 , G06F17/505 , H03K19/1737
摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.
摘要翻译：对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系（PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

55. 发明授权

US5872716A Semiconductor integrated logic circuit device using a pass transistor 失效
公开(公告)号：US5872716A
公开(公告)日：1999-02-16
申请号：US703189
申请日：1996-08-26
申请人： Kazuo Yano , Yasuhiko Sasaki
发明人： Kazuo Yano , Yasuhiko Sasaki
IPC分类号： H01L21/82 , H01L27/02 , H01L27/118 , H03K19/173 , G06F13/00
CPC分类号： H03K19/1735 , H01L27/0207 , H01L27/11807 , H01L2924/14
摘要： The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.

56. 发明授权

US5371023A Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor 失效
标题翻译：门电路，半导体集成电路器件及其制造方法，半导体存储器和微处理器
公开(公告)号：US5371023A
公开(公告)日：1994-12-06
申请号：US895815
申请日：1992-06-09
申请人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
发明人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
IPC分类号： H01L27/06 , H01L27/105 , H01L21/20
CPC分类号： H01L27/105 , H01L27/0623
摘要： A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.
摘要翻译：公开了一种新颖的门电路。第一半导体开关包括连接在第一电位电平和输出节点之间的一对主端子，其中响应于具有第一逻辑电平和第二逻辑电平的输入信号而保持高阻抗状态，并且阻抗状态仅在输入信号从第一逻辑电平变化到第二逻辑电平的过渡期间从高变化为低电平。第二半导体开关包括插入在与第一电位电平不同的第二电位电平和输出节点之间的一对主端子，其中响应于输入信号保持高阻抗状态，并且阻抗状态从高变为仅在输入信号从第二逻辑电平变为第一逻辑电平的瞬态期间为低电平。

57. 发明授权

US5148387A Logic circuit and data processing apparatus using the same 失效
标题翻译：逻辑电路及使用其的数据处理装置
公开(公告)号：US5148387A
公开(公告)日：1992-09-15
申请号：US480674
申请日：1990-02-15
申请人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
发明人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
IPC分类号： G06F7/50 , G06F7/501
CPC分类号： G06F7/5016
摘要： A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.
摘要翻译：逻辑电路包括第一，第二，第三，第四，第五和第六场效应晶体管或FET，输入节点和输出节点。第五和第六FET连接到输出节点。第一和第三FET连接到第五FET。第二和第四FET连接到第六FET。第一和第二FET连接到第一输入节点。第三和第四FET连接到第二节点。第一信号被提供给第一输入节点。向第一和第四FET的栅电极提供第二信号。具有与第二信号相反的相位的信号被提供给第二和第三FET的栅电极。第三信号被提供给第二输入节点。从第一，第二和第三信号中选择的一个信号被提供给第五FET的栅电极。具有与提供给第五FET的栅电极的信号相反的相位的信号被提供给第六FET的栅电极。从输出节点生成与第一，第二和第三输入信号有关的输出信号。输出信号例如是进位输出信号或多数决定逻辑输出信号。

58. 发明授权

US4864382A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4864382A
公开(公告)日：1989-09-05
申请号：US148052
申请日：1988-01-25
申请人： Masaaki Aoki , Kazuo Yano , Toshiaki Masuhara
发明人： Masaaki Aoki , Kazuo Yano , Toshiaki Masuhara
IPC分类号： H01L27/108 , H01L29/10 , H01L29/167 , H01L29/66
CPC分类号： H01L29/66992 , H01L27/10805 , H01L29/1083 , H01L29/167 , Y10S257/919
摘要： A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.
摘要翻译：在半导体本体中形成MOS存储器，而在MOS存储器部分和半导体体之间的边界处设置阻挡半导体层，以便降低由α-粒子激发的不希望的载流子的影响。阻挡半导体层被设计为允许在低温下操作存储器，同时减少由于α-粒子引起的软错误的发生。

59. 发明申请

US20120158464A1 VISUALIZATION SYSTEM FOR ORGANIZATIONAL COMMUNICATION 审中-公开
标题翻译：组织沟通可视化系统
公开(公告)号：US20120158464A1
公开(公告)日：2012-06-21
申请号：US13405913
申请日：2012-02-27
申请人： Satomi TSUJI , Kazuo Yano , Nobuo Sato
发明人： Satomi TSUJI , Kazuo Yano , Nobuo Sato
IPC分类号： G06Q10/06
CPC分类号： G06Q10/00 , G06Q10/063 , G06Q10/0639
摘要： To provide a visualization method for analyzing the condition of an organization, the condition of a sub-organization, and the condition of an individual, with the face-to-face contact communication between members belonging to an organization being used as a cross section. A sensor-net system comprises a plurality of terminals and a processing unit that processes data sent from the plurality of terminals, wherein the each terminal comprises: a sensor for detecting a physical quantity; and a data sender unit that sends data indicative of the physical quantity detected by the sensor, and wherein based on the data sent from a first terminal, the processing unit plots this data on a coordinate plane consisting of two axes, in which an intensity of a relation, which a first person equipped with the first terminal has with other person, is assigned to one axis and a diversity of the relation is assigned to the other axis.
摘要翻译：提供一种用于分析组织状况，子组织状况和个人情况的可视化方法，并将属于组织的成员之间的面对面联系通信用作横截面。传感器网络系统包括多个终端和处理从多个终端发送的数据的处理单元，其中每个终端包括：用于检测物理量的传感器; 以及数据发送器单元，发送指示由所述传感器检测到的物理量的数据，并且其中，基于从第一终端发送的数据，所述处理单元将该数据绘制在由两个轴组成的坐标平面上，其中，将配备有第一终端的第一人与其他人相关联的关系被分配给一个轴，并且该关系的多样性被分配给另一个轴。

60. 发明申请

US20120092379A1 SENSING DATA DISPLAY APPARATUS AND SENSING DATA PROCESSING SYSTEM 审中-公开
标题翻译：感应数据显示设备和感应数据处理系统
公开(公告)号：US20120092379A1
公开(公告)日：2012-04-19
申请号：US13271325
申请日：2011-10-12
申请人： Satomi TSUJI , Nobuo Sato , Kazuo Yano , Koji Ara , Tomoaki Akitomi , Rieko Otsuka
发明人： Satomi TSUJI , Nobuo Sato , Kazuo Yano , Koji Ara , Tomoaki Akitomi , Rieko Otsuka
IPC分类号： G09G5/00 , G06F15/16
CPC分类号： G06Q10/06 , G06Q10/10
摘要： It is provided a sensing data display apparatus which displays a sensing data with regard to a human, the sensing data display apparatus comprising: a receiving module for receiving a data indicating a physical amount detected by a sensor terminal mounted by the human; a sensing data storing module for storing the data indicating the physical amount; an information creating module for creating a piece of information related to the sensor terminal from the data stored to the sensing data storing module; a display module for displaying the piece of information; and a viewer detecting module for detecting a viewer who locates at a vicinity of the sensing display apparatus. The display module displays the piece of information related to a piece of information of the viewer detected by the viewer detecting module.
摘要翻译：提供了一种感测数据显示装置，其显示关于人的感测数据，所述感测数据显示装置包括：接收模块，用于接收指示由人安装的传感器终端检测到的物理量的数据; 感测数据存储模块，用于存储指示物理量的数据; 信息创建模块，用于从存储到感测数据存储模块的数据创建与传感器终端相关的信息; 用于显示该信息的显示模块; 以及观察器检测模块，用于检测位于感测显示装置附近的观看者。显示模块显示与由观看者检测模块检测到的观看者的一条信息相关的信息。

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